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1999, 2001 data sheet mos integrated circuits 16-bit single-chip microcontrollers pd784935a,784936a,784937a,784938a document no. u13572ej2v0ds00 date published january 2001 n cp(k) printed in japan description the pd784935a, 784936a, 784937a, and 784938a are members of the pd784938a subseries in the 78k/iv series. these microcontrollers are based on the pd784908 subseries but are provided with the higher internal rom and ram capacities and a rom correction function. in addition, a flash memory version, pd78f4938a, that can operate in the same power supply voltage range as the mask rom version, and various development tools are also available. detailed function descriptions are provided in the following users manuals. be sure to read them before designing. pd784938a subseries users manual - hardware: u13987e 78k/iv series users manual - instructions: u10905e features 78k/iv series minimum instruction execution time: 320 ns (fxx = 6.29 mhz) 160 ns (fxx = 12.5 mhz) i/o ports: 80 pins timers/counters: 16-bit timer/event counter 1 unit 8-/16-bit timer/event counter 2 units 8-/16-bit timer 1 unit serial interface: 4 channels uart/ioe (3-wire serial i/o): 2 channels csi (3-wire serial i/o): 2 channels pwm output: 2 outputs standby function halt/stop/idle mode clock division function external expansion function internal rom correction function watchdog timer: 1 channel clock output function: selectable from f clk , f clk /2, f clk /4, f clk /8, and f clk /16 a/d converter: 8-bit resolution 8 channels iebus tm controller watch timer low power consumption supply voltage: ? dd = 4.0 to 5.5 v (@12.58 mhz operation) ? dd = 3.0 to 5.5 v (@6.29 mhz operation) application car audio, etc. unless otherwise specified, the pd784938a is treated as the representative model in this document. the mark shows major revised points. the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information.
pd784935a,784936a,784937a,784938a 2 data sheet u13572ej2v0ds ordering information part number package internal rom (bytes) internal ram (bytes) pd784935agf- -3ba 100-pin plastic qfp (14 20) 96 kb 5120 bytes pd784936agf- -3ba 100-pin plastic qfp (14 20) 128 kb 6656 bytes pd784937agf- -3ba 100-pin plastic qfp (14 20) 192 kb 8192 bytes pd784938agf- -3ba 100-pin plastic qfp (14 20) 256 kb 10496 bytes remark indicates rom code suffix.
3 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a 78k/iv series product development pd784026 pd784956a pd784908 pd784915 pd784928 pd784928y pd784046 pd784054 pd784216a pd784216ay pd784038 pd784038y pd784225y pd784225 pd784218ay pd784218a enhanced a/d converter, 16-bit timer, and power management enhanced internal memory capacity pin-compatible with the pd784026 supports i 2 c bus supports multimaster i 2 c bus 80-pin, rom correction added supports multimaster i 2 c bus enhanced internal memory capacity, rom correction added 100-pin, enhanced i/o and internal memory capacity on-chip 10-bit a/d converter for dc inverter control on-chip iebus tm controller software servo control on-chip analog circuit for vcrs enhanced timer supports multimaster i 2 c bus enhanced functions of the pd784915 standard models assp models supports multimaster i 2 c bus : products in mass-production : products under development pd784976a on-chip vfd controller/driver pd784938a enhanced functions of the pd784908, enhanced internal memory capacity, rom correction added. pd784967 enhanced functions of the pd784938a, enhanced i/o and internal memory capacity. enhanced peripheral functions
pd784935a,784936a,784937a,784938a 4 data sheet u13572ej2v0ds function list (1/2) part number pd784935a pd784936a pd784937a pd784938a item number of basic instructions (mnemonics) 113 general-purpose registers 8 bits 32 registers 8 banks, or 16 bits 8 registers 8 banks (memory map) minimum instruction execution time 320 ns/636 ns/1.27 s/2.54 s (@6.29 mhz operation) 160 ns/320 ns/636 ns/1.27 s (@12.58 mhz operation) internal memory rom 96 kb 128 kb 192 kb 256 kb ram 5120 bytes 6656 bytes 8192 bytes 10496 bytes memory space 1 mb with program and data spaces combined i/o port total 80 pins input 8 pins i/o 72 pins pins with led direct drive output 24 pins ancillary transistor direct drive 8 pins function note n-ch open drain drive 4 pins real-time output port 4 bits 2, or 8 bits 1 iebus controller internal (simple version) timer/counter timer/event counter 0: timer counter 1 pulse output possible (16 bits) capture register 1 toggle output compare register 2 pwm/ppg output one-shot pulse output timer/event counter 1: timer counter 1 real-time output port (16 bits) capture register 1 capture/compare register 1 compare register 1 timer/event counter 2: timer counter 1 pulse output possible (16 bits) capture register 1 toggle output capture/compare register 1 pwm/ppg output compare register 1 timer 3 (16 bits): timer counter 1 compare register 1 watch timer generates interrupt request at 0.5-second intervals (internal watch clock oscillator provided) main clock (12.58 mhz) or watch clock (32.7 khz) selectable as input clock clock output selectable from f clk , f clk /2, f clk /4, f clk /8, or f clk /16 (also usable as 1-bit output port) pwm output 12-bit resolution 2 channels serial interface uart/ioe (3-wire serial i/o): 2 channels (with internal baud rate generator) csi (3-wire serial i/o): 2 channels a/d converter 8-bit resolution 8 channels watchdog timer 1 channel rom correction function internal (4 points of correction addresses can be set.) external expansion function provided (up to 1 mb) note pins with ancillary functions are included in the i/o pins.
5 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a (2/2) part number pd784935a pd784936a pd784937a pd784938a item standby halt/stop/idle mode interrupt hardware source 27 (internal: 20, external: 7 (sampling clock variable input: 1)) software source brk instruction, brkcs instruction, operand error non-maskable internal: 1, external: 1 maskable internal: 19, external: 6 four programmable priority levels three types of processing formats: vectored interrupt/macro service/context switching supply voltage v dd = 4.0 to 5.5 v (@12.58 mhz operation) v dd = 3.0 to 5.5 v (@6.29 mhz operation) package 100-pin plastic qfp (14 20)
pd784935a,784936a,784937a,784938a 6 data sheet u13572ej2v0ds contents 1. differences between products in pd784938a subseries .............................. 8 2. major differences between pd784908, pd784038, and pd78098 subseries ...................................................................................................................... .............. 9 3. pin configuration (top view) .............................................................................................. 10 4. system configuration example (car audio system (tuner and deck)) .................... 12 5. block diagram ......................................................................................................................... 13 6. pin functions ............................................................................................................................ 14 6.1 port pins ............................................................................................................................... .. 14 6.2 non-port pins ........................................................................................................................ 16 6.3 pin i/o circuits and recommended connection of unused pins .................................. 18 7. cpu architecture ................................................................................................................... 22 7.1 memory space ....................................................................................................................... 22 7.2 cpu registers ....................................................................................................................... 27 7.2.1 general-purpose registers .......................................................................................................... 27 7.2.2 control registers .......................................................................................................................... 28 7.2.3 special function registers (sfrs) ............................................................................................... 29 8. peripheral hardware functions ................................................................................... 34 8.1 ports ....................................................................................................................... ................. 34 8.2 clock generator .................................................................................................................... 36 8.3 real-time output port .......................................................................................................... 39 8.4 timers/counters .................................................................................................................... 40 8.5 watch timer ........................................................................................................................... 42 8.6 pwm output (pwm0, pwm11) ............................................................................................ 43 8.7 a/d converter ........................................................................................................................ 44 8.8 serial interface ...................................................................................................................... 45 8.8.1 asynchronous serial interface/3-wire serial i/o (uart/ioe) .................................................... 46 8.8.2 clocked serial interface (csi) ..................................................................................................... 48 8.9 clock output function ......................................................................................................... 49 8.10 edge detection function ..................................................................................................... 50 8.11 watchdog timer ..................................................................................................................... 50 8.12 simplified iebus controller ................................................................................................. 51 9. interrupt function ............................................................................................................... 54 9.1 interrupt sources .................................................................................................................. 54 9.2 vectored interrupt ................................................................................................................. 56 9.3 context switching ................................................................................................................. 57 9.4 macro service ........................................................................................................................ 57 9.5 application examples of macro service ............................................................................ 58
7 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a 10. local bus interface ............................................................................................................ 60 10.1 memory expansion ............................................................................................................... 60 10.2 memory space ....................................................................................................................... 61 10.3 programmable wait ............................................................................................................... 62 10.4 pseudo static ram refresh function ............................................................................... 62 10.5 bus hold function ................................................................................................................ 62 11. standby function ................................................................................................................... 63 12. reset function ........................................................................................................................ 64 13. regulator ............................................................................................................................... .... 65 14. rom correction ...................................................................................................................... 66 15. instruction set ....................................................................................................................... 67 16. electrical specifications .................................................................................................. 72 17. package drawings .................................................................................................................. 92 18. recommended soldering conditions ........................................................................... 93 appendix a. development tools ............................................................................................ 94 appendix b. related documents ........................................................................................... 97
pd784935a,784936a,784937a,784938a 8 data sheet u13572ej2v0ds 1. differences between products in pd784938a subseries the only difference between the pd784935a, 784936a, 784937a, and 784938a is the internal memory capacity. the pd78f4938a has a 256 kb flash memory in the place of the mask rom of the above models. table 1-1 shows the differences between these models. table 1-1. differences between products in pd784938a subseries part number pd784935a pd784936a pd784937a pd784938a pd78f4938a item internal rom 96 kb 128 kb 192 kb 256 kb mask rom flash memory internal ram 5120 bytes 6656 bytes 8192 bytes 10496 bytes regulator provided none electrical specifications refer to the data sheet of each product. internal memory size none provided switching register note ic pin provided none v pp pin none provided note the internal flash memory capacity and internal ram capacity can be changed by using the internal memory size switching register (ims).
9 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a 2. major differences between pd784908, pd784038, and pd78098 subseries series name pd784938a subseries pd784908 subseries pd784038 subseries pd78098 subseries item number of basic 113 63 instructions (mnemonics) minimum instruction 160 ns 125 ns 480 ns execution time (@12.5 mhz operation, internally) (@32 mhz operation) (@6.29 mhz operation) memory space 1 mb 60 kb (program data) timer/counter 16-bit timer/event counter 1 16-bit timer/ 16-bit timer/ 8-/16-bit timer/event counter 2 event counter 1 event counter 1 8-/16-bit timer 1 8-/16-bit timer/ 8-bit timer/ watch timer event counter 2 event counter 2 8-/16-bit timer 1 watch timer single clock single clock dual clock watch clock provided for watch operation. serial interface uart/ioe (3-wire serial i/o): 2 channels uart/ioe (3-wire uart (3-wire serial (baud rate generator) serial i/o): 2 channels i/o): 1 channel csi (3-wire serial i/o): 2 channels csi (3-wire serial i/o, csi/sbi (3-wire serial 2-wire serial i/o): i/o): 1 channel 1 channel csi (3-wire serial i/o): 1 channel pwm output 12-bit resolution 2 channels none d/a converter none 8-bit resolution 2 channels interrupt hardware source 27 sources 24 sources 23 sources (with two test flags) internal 20 sources 17 sources 14 sources external 7 sources 7 sources 7 sources external expansion function provided (up to 1 mb) none iebus controller internal (simple version) not provided internal (complete hardware) rom correction internal not provided (4 points can be set.) supply voltage v dd = 4.0 to 5.5 v v dd = 3.5 to 5.5 v v dd = 2.7 to 5.5 v v dd = 2.7 to 6.0 v (mask rom versions) v dd = 4.0 to 5.5 v (prom versions) package 100-pin plastic qfp 100-pin plastic qfp 80-pin plastic qfp 80-pin plastic tqfp (14 20) (14 20) (14 14) (fine pitch) (14 14) 80-pin plastic tqfp 80-pin plastic wqfn (fine pitch) (14 14) (14 14): 80-pin plastic wqfn pd78p098a only (14 14): pd78p4038 only note pins with ancillary functions are included in the i/o pins.
pd784935a,784936a,784937a,784938a 10 data sheet u13572ej2v0ds 3. pin configuration (top view) 100-pin plastic qfp (14 20) pd784935agf- -3ba pd784936agf- -3ba pd784937agf- -3ba pd784938agf- -3ba 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 p36/t02 p37/t03 p100 p101 p102 p103 p104 p105/sck3 p106/si3 p107/so3 reset xt2 xt1 v ss x2 x1 regoff regc v dd p00 p01 p02 p03 p04 p05 p06 p07 p67/refrq/hldak p66/wait/hldrq p65/wr p76/ani6 p75/ani5 p74/ani4 p73/ani3 p72/ani2 p71/ani1 p70/ani0 ic pwm1 pwm0 p17 p16 p15 p14/txd2/so2 p13/rxd2/si2 p12/asck2/sck2 p11 p10 astb/clkout p90 p91 p92 p93 p94 p95 p96 p97 p40/ad0 p41/ad1 p42/ad2 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p35/to1 p34/to0 p33/so0 p32/sck0 p31/txd/so1 p30/rxd/si1 p27/si0 p26/intp5 p25/intp4/asck/sck1 p24/intp3 p23/intp2/ci p22/intp1 p21/intp0 p20/nmi tx rx av ss av ref1 av dd p77/ani7 p64/rd p63/a19 p62/a18 p61/a17 p60/a16 p57/a15 p56/a14 p55/a13 p54/a12 v ss v dd p53/a11 p52/a10 p51/a9 p50/a8 p47/ad7 p46/ad6 p45/ad5 p44/ad4 p43/ad3 cautions 1. connect the ic (internally connected) pin directly to v ss . 2. connect the av dd pin directly to v dd . 3. connect the av ss pin directly to v ss .
11 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a a8 to a19: address bus ad0 to ad7: address/data bus ani0 to ani7: analog input asck, asck2: asynchronous serial clock astb: address strobe av dd : analog power supply av ref1 : reference voltage av ss : analog ground ci: clock input clkout: clock output hldak: hold acknowledge hldrq: hold request ic: internally connected intp0 to intp5: interrupt from peripherals nmi: non-maskable interrupt p00 to p07: port0 p10 to p17: port1 p20 to p27: port2 p30 to p37: port3 p40 to p47: port4 p50 to p57: port5 p60 to p67: port6 p70 to p77: port7 p90 to p97: port9 p100 to p107: port10 pwm0, pwm1: pulse width modulation output rd: read strobe refrq: refresh request regc: regulator capacitance regoff: regulator off reset: reset rx: iebus receive data rxd, rxd2: receive data sck0 to sck3: serial clock si0 to si3: serial input so0 to so3: serial output to0 to to3: timer output tx: iebus transmit data txd, txd2: transmit data v dd : power supply v ss : ground wait: wait wr: write strobe x1, x2: crystal (main system clock) xt1, xt2: crystal (watch)
pd784935a,784936a,784937a,784938a 12 data sheet u13572ej2v0ds 4. system configuration example (car audio system (tuner and deck)) remote controller signal receiver fip tm led display fip controller/driver key matrix audio system control circuit electronic volume eeprom tm pd16312, etc. pc2800a, etc. front panel pd784938a interrupt input general- purpose port 3-wire serial i/o iebus controller sio with automatic transmit/receive function 3-wire serial i/o cassette deck unit tuner pack iebus driver/ receiver iebus cd unit changer, single cd, etc. dsp unit tv unit
13 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a 5. block diagram remark the internal rom and ram capacities vary depending on the product. programmable interrupt controller timer/counter 0 (16 bits) timer/counter 1 (16 bits) timer/counter 2 (16 bits) timer 3 (16 bits) real-time output port pwm a/d converter 78k/iv cpu core rom ram watchdog timer uart/ioe 2 baud-rate generator uart/ioe 1 baud-rate generator clocked serial interface clock output bus i/f port 0 port 1 port 2 port 3 port 4 port 5 port 6 port 7 nmi intp0 to intp5 intp3 to0 to1 intp0 intp1 intp2/ci to2 to3 p00 to p03 p04 to p07 pwm0 pwm1 iebus controller tx rx ani0 to ani7 av dd av ref1 av ss intp5 rxd/si1 txd/so1 asck/sck1 rxd2/si2 txd2/so2 asck2/sck2 sck0 so0 si0 clocked serial interface 3 sck3 so3 si3 astb/clkout ad0 to ad7 a8 to a15 a16 to a19 rd wr wait/hldrq refrq/hldak p00 to p07 p10 to p17 p20 to p27 p30 to p37 p40 to p47 p50 to p57 p60 to p67 p70 to p77 port 9 port 10 p90 to p97 p100 to p107 watch timer xt1 xt2 reset ic x1 x2 regc regoff v dd v ss system control (regulator)
pd784935a,784936a,784937a,784938a 14 data sheet u13572ej2v0ds 6. pin functions 6.1 port pins (1/2) pin name i/o alternate function function p00 to p07 input/ output p10 input/ p11 output p12 asck2/sck2 p13 rxd2/si2 p14 txd2/so2 p15 to 17 p20 input nmi p21 intp0 p22 intp1 p23 intp2/ci p24 intp3 p25 intp4/asck/sck1 p26 intp5 p27 si0 p30 input/ rxd/si1 p31 output txd/so1 p32 sck0 p33 so0 p34 to p37 to0 to to3 p40 to p47 input/ ad0 to ad7 output p50 to p57 input/ a8 to a15 output p60 to p63 input/ a16 to a19 p64 output rd p65 wr p66 wait/hldrq p67 refrq/hldak port 0 (p0): 8-bit i/o port. can be used as real-time output port (4 bits 2). input/output can be specified in 1-bit units. an on-chip pull-up resistor can be specified by means of software for pins in input mode. can drive transistor. port 1 (p1): 8-bit i/o port. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be specified by means of software for pins in input mode. can drive led. port 2 (p2): 8-bit input port. p20 cannot be used as general-purpose port pin (non-maskable interrupt). however, input level can be checked by interrupt routine. an on-chip pull-up resistor can be specified for p22 to p27 by means of software in 6-bit units. p25/intp4/asck/sck1 pin operates as sck1 i/o pin if so specified by csim1. port 3 (p3): 8-bit i/o port. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be specified by means of software for pins in input mode. p32 and p33 can be specified for n-ch open-drain connection. port 5 (p5): 8-bit i/o port. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be specified by means of software for pins in input mode. can drive led. port 4 (p4): 8-bit i/o port. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be specified by means of software for pins in input mode. can drive led. port 6 (p6): 8-bit i/o port. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be specified by means of software for pins in input mode.
15 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a 6.1 port pins (2/2) pin name i/o alternate function function p70 to p77 input/ ani0 to ani7 output p90 to p97 input/ output p100 to p104 input/ p105 output sck3 p106 si3 p107 so3 port 7 (p7): 8-bit i/o port. input/output can be specified in 1-bit units. port 9 (p9): 8-bit i/o port. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be specified by means of software for pins in input mode. port 10 (p10): 8-bit i/o port. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be specified by means of software for pins in input mode. p105 and p107 can be specified for n-ch open-drain connection.
pd784935a,784936a,784937a,784938a 16 data sheet u13572ej2v0ds 6.2 non-port pins (1/2) pin name i/o alternate function function to0 to to3 output p34 to p37 timer output ci input p23/intp2 count clock input to timer/counter 2 rxd input p30/si1 serial data input (uart0) rxd2 p13/si2 serial data input (uart2) txd output p31/so1 serial data output (uart0) txd2 p14/so2 serial data output (uart2) asck input p25/intp4/sck1 baud rate clock input (uart0) asck2 p12/sck2 baud rate clock input (uart2) si0 input p27 serial data input (3-wire serial i/o0) si1 p30/rxd serial data input (3-wire serial i/o1) si2 p13/rxd2 serial data input (3-wire serial i/o2) si3 p106 serial data input (3-wire serial i/o3) so0 output p33 serial data output (3-wire serial i/o0) so1 p31/txd serial data output (3-wire serial i/o1) so2 p14/txd2 serial data output (3-wire serial i/o2) so3 p107 serial data output (3-wire serial i/o3) sck0 input/ p32 serial clock input/output (3-wire serial i/o0) sck1 output p25/intp4/asck serial clock input/output (3-wire serial i/o1) sck2 p12/asck2 serial clock input/output (3-wire serial i/o2) sck3 p105 serial clock input/output (3-wire serial i/o3) nmi input p20 external interrupt requests intp0 p21 count clock input to timer/counter 1 capture trigger signal of cr11 or cr12 intp1 p22 count clock input to timer/counter 2 capture trigger signal of cr22 intp2 p23/ci count clock input to timer/counter 2 capture trigger signal of cr21 intp3 p24 count clock input to timer/counter 0 capture trigger signal of cr02 intp4 p25/asck/sck1 intp5 p26 conversion start trigger input of a/d converter ad0 to ad7 input/ p40 to p47 time-division address/data bus (external memory connection) output a8 to a15 output p50 to p57 higher address bus (external memory connection) a16 to a19 output p60 to p63 higher address for address extension (external memory connection) rd output p64 read strobe to external memory wr output p65 write strobe to external memory wait input p66/hldrq wait insertion refrq output p67/hldak refresh pulse output to external pseudo-static memory hldrq input p66/wait bus hold request input hldak output p67/refrq bus hold acknowledge output astb output clkout latch timing output of time-division address (a0 to a7) (when external memory is accessed)
17 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a 6.2 non-port pins (2/2) pin name i/o alternate function function clkout output astb clock output pwm0 output pwm output 0 pwm1 output pwm output 1 rx input data input (iebus) tx output data output (iebus) regc capacitor connection for regulation output stabilization/power supply when regulator is stopped regoff regulator operation specification signal reset input chip reset x1 input crystal connection for system clock oscillation (clock can be also input to x1.) x2 xt1 input watch clock connection xt2 ani0 to ani7 input p70 to p77 analog voltage input for a/d converter av ref1 application of reference voltage for a/d converter av dd positive power supply for a/d converter av ss gnd for a/d converter v dd positive power supply v ss gnd ic input internally connected. connect this pin directly to v ss (this pin is used to test the ic.)
pd784935a,784936a,784937a,784938a 18 data sheet u13572ej2v0ds 6.3 pin i/o circuits and recommended connection of unused pins the input/output circuit type of each pin and recommended connection of unused pins are shown in table 6-1. for the input/output circuit configuration of each type, refer to figure 6-1 . table 6-1. types of pin input/output circuits (1/2) pin name input/output circuit type i/o recommended connection of unused pins p00 to p07 5-a input/output input: connect to v dd . p10, p11 output: leave open. p12/asck2/sck2 8-a p13/rxd2/si2 5-a p14/txd2/so2 p15 to p17 p20/nmi 2 input connect to v dd or v ss . p21/intp0 p22/intp1 2-a connect to v dd . p23/intp2/ci p24/intp3 p25/intp4/asck/sck1 8-a input/output input: connect to v dd . output: leave open. p26/intp5 2-a input connect to v dd . p27/si0 p30/rxd/si1 5-a input/output input: connect to v dd . p31/txd/so1 output: leave open. p32/sck0 10-a p33/so0 p34/to0 to p37/to3 5-a p40/ad0 to p47/ad7 p50/a8 to p57/a15 p60/a16 to p63/a19 p64/rd p65/wr p66/wait/hldrq p67/refrq/hldak p70/ani0 to p77/ani7 20 input/output input: connect to v dd or v ss . p90 to p97 5-a output: leave open. p100 to p104 p105/sck3 10-a p106/si3 8-a p107/so3 10-a astb/clkout 4 output leave open. reset 2 input ic 1 connect directly to v ss . xt2 leave open. xt1 input connect directly to v ss .
19 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a table 6-1. types of pin input/output circuits (2/2) pin name input/output circuit type i/o recommended connection of unused pins regoff 1 connect directly to v dd . regc connect to v dd . pwm0, pwm1 3 output leave open. rx 1 input connect to v dd or v ss . tx 3 output leave open. av ref1 connect to v ss . av ss av dd connect to v dd . caution connect an i/o pin to v dd via a resistor of several 10 k ? if the i/o mode of the pin is unstable (especially if the voltage on the reset pin is higher than the low-level input voltage on power application or if the mode is changed between input and output by software). remark the circuit type numbers are common for the 78k series and are not always sequential for one product (some circuits are not provided).
pd784935a,784936a,784937a,784938a 20 data sheet u13572ej2v0ds figure 6-1. pin input/output circuits (1/2) type 2 schmitt triggered input with hysteresis characteristics type 1 type 4 push-pull output that can go into a high-impedance state (both p-ch and n-ch are off). type 5-a p in v dd n in data output disable p out v dd n data output disable p in/out v dd n input enable p v dd pull-up enable type 2-a schmitt triggered input with hysteresis characteristics in p v dd pull-up enable type 8-a type 10-a data output disable p in/out v dd n p v dd pull-up enable data output disable p in/out v dd n p v dd pull-up enable open-drain type 3 p-ch out data v dd n-ch
21 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a type 20 data output disable p in/out v dd n input enable comparator + p n v ref (threshold voltage) figure 6-1. pin input/output circuits (2/2)
pd784935a,784936a,784937a,784938a 22 data sheet u13572ej2v0ds 7. cpu architecture 7.1 memory space a memory space of 1 mb can be accessed. mapping of the internal data area (special function registers and internal ram) can be selected by using the location instruction. the location instruction must be always executed after the reset signal has been cleared, and must not be used more than once. (1) when location 0h instruction is executed internal memory the internal data area and internal rom area are as follows: part number internal data area internal rom area pd784935a 0eb00h to 0ffffh 00000h to 0eaffh 10000h to 17fffh pd784936a 0e500h to 0ffffh 00000h to 0e4ffh 10000h to 1ffffh pd784937a 0df00h to 0ffffh 00000h to 0deffh 10000h to 2ffffh pd784938a 0d600h to 0ffffh 00000h to 0d5ffh 10000h to 3ffffh caution the following area of the internal rom that overlaps the internal data area cannot be used when the location 0h instruction is executed. part number unusable area pd784935a 0eb00h to 0ffffh (5376 bytes) pd784936a 0e500h to 0ffffh (6192 bytes) pd784937a 0df00h to 0ffffh (8448 bytes) pd784938a 0d600h to 0ffffh external memory the external memory is accessed in the external memory expansion mode. (2) when location 0fh instruction is executed internal memory the internal data area and internal rom area are as follows: part number internal data area internal rom area pd784935a feb00h to fffffh 00000h to 17fffh pd784936a fe500h to fffffh 00000h to 1ffffh pd784937a fdf00h to fffffh 00000h to 2ffffh pd784938a fd600h to fffffh 00000h to 3ffffh external memory the external memory is accessed in the external memory expansion mode.
23 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a figure 7-1. memory map of pd784935a notes 1. accessed in the e xternal memory expansion mode. 2. 5376 bytes in this area can be used as an inter nal rom area only when the loca tion 0fh instruction is executed. 3. when location 0h instruction is executed: 92928 bytes, when location 0fh instruction is executed: 98304 bytes 4. base area, or entr y area used in the case of reset or interr upt. however, the internal ram is excluded in the case of reset. note 4 note 4 fffffh fffdfh fffd0h fff00h ffeffh feb00h feaffh 18000h 17fffh 00000h 0feffh 0fe80h 0fe7fh 00800h 007ffh 00000h 0fe39h 0fe06h 0fd00h 0fcffh 0eb00h 17fffh 01000h 00fffh 00080h 0007fh 00040h 0003fh 0eb00h 0eaffh 00000h ffeffh ffe80h ffe7fh ffe39h ffe06h ffd00h ffcffh feb00h fffffh 10000h 0ffffh 0ffdfh 0ffd0h 0ff00h 0feffh 17fffh 18000h 17fffh 10000h 0eaffh (256 bytes) special function register (sfr) internal rom (60160 bytes) internal ram (5120 bytes ) external memory note 1 (928 kb) note 1 general-purpose register (128 bytes) macro service control word area (42 bytes) data area (512 bytes) program/data area (4608 bytes) note 2 callf entry area (2 kb) program/data area note 3 callt table area (64 bytes) vector table area (64 bytes) internal ram (5120 bytes) external memory note 1 (944896 bytes) (256 bytes) special function register (sfr) internal rom (96 kb) w hen location 0h instruction is executed note 1 when location 0fh instruction is executed internal rom (32768 bytes)
pd784935a,784936a,784937a,784938a 24 data sheet u13572ej2v0ds figure 7-2. memory map of pd784936a notes 1. accessed in the e xternal memory expansion mode. 2. 6912 bytes in this area can be used as an inter nal rom area only when the loca tion 0fh instruction is executed. 3. when location 0h instruction is executed: 124160 bytes, when location 0fh instruction is executed: 131072 bytes 4. base area, or entr y area used in the case of reset or interr upt. however, the internal ram is excluded in the case of reset. (256 bytes) special function register (sfr) internal rom (58624 bytes) internal ram (6656 bytes ) external memory note 1 (896 kb) note 1 general-purpose register (128 bytes) macro service control word area (42 bytes) data area (512 bytes) program/data area (6144 bytes) note 2 callf entry area (2 kb) program/data area note 3 callt table area (64 bytes) vector table area (64 bytes) internal ram (6656 bytes) external memory note 1 (910720 bytes) (256 bytes) special function register (sfr) internal rom (128 kb) note 4 note 4 when location 0h instruction is executed fffffh fffdfh fffd0h fff00h ffeffh fe500h fe4ffh 20000h 1ffffh 00000h 0feffh 0fe80h 0fe7fh 00800h 007ffh 00000h 0fe39h 0fe06h 0fd00h 0fcffh 0e500h 1ffffh 01000h 00fffh 00080h 0007fh 00040h 0003fh 0e500h 0e4ffh 00000h ffeffh ffe80h ffe7fh ffe39h ffe06h ffd00h ffcffh fe500h note 1 when location 0fh instruction is executed fffffh 10000h 0ffffh 0ffdfh 0ffd0h 0ff00h 0feffh 1ffffh internal rom (65536 bytes) 20000h 1ffffh 10000h 0e4ffh
25 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a figure 7-3. memory map of pd784937a notes 1. accessed in the e xternal memory expansion mode. 2. 8448 bytes in this area can be used as an inter nal rom area only when the loca tion 0fh instruction is executed. 3. when location 0h instruction is executed: 188160 bytes, when location 0fh instruction is executed: 196608 bytes 4. base area, or entr y area used in the case of reset or interr upt. however, the internal ram is excluded in the case of reset. note 4 note 4 fffffh fffdfh fffd0h fff00h ffeffh fdf00h fdeffh 30000h 2ffffh 00000h 0feffh 0fe80h 0fe7fh 00800h 007ffh 00000h 0fe39h 0fe06h 0fd00h 0fcffh 0df00h 2ffffh 01000h 00fffh 00080h 0007fh 00040h 0003fh 0df00h 0deffh 00000h ffeffh ffe80h ffe7fh ffe39h ffe06h ffd00h ffcffh fdf00h fffffh 10000h 0ffffh 0ffdfh 0ffd0h 0ff00h 0feffh 2ffffh 30000h 2ffffh 10000h 0deffh (256 bytes) special function register (sfr) internal rom (57088 bytes) internal ram (8192 bytes ) external memory note 1 (832 kb) note 1 general-purpose register (128 bytes) macro service control word area (42 bytes) data area (512 bytes) program/data area (7680 bytes) note 2 callf entry area (2 kb) program/data area note 3 callt table area (64 bytes) vector table area (64 bytes) internal ram (8192 bytes) external memory note 1 (843520 bytes) (256 bytes) special function register (sfr) internal rom (192 kb) when location 0h instruction is executed note 1 when location 0fh instruction is executed internal rom (131072 bytes)
pd784935a,784936a,784937a,784938a 26 data sheet u13572ej2v0ds figure 7-4. memory map of pd784938a notes 1. accessed in the e xternal memory expansion mode. 2. 10752 bytes in this area can be used as an inter nal rom area only when the loca tion 0fh instruction is executed. 3. when location 0h instruction is executed: 251392 bytes, when location 0fh instr uction is executed: 262144 bytes 4. base area, or entr y area used in the case of reset or interr upt. however, the internal ram is excluded in the case of reset. note 4 note 4 fffffh fffdfh fffd0h fff00h ffeffh fd600h fd5ffh 40000h 3ffffh 00000h 0feffh 0fe80h 0fe7fh 00800h 007ffh 00000h 0fe39h 0fe06h 0fd00h 0fcffh 0d600h 3ffffh 01000h 00fffh 00080h 0007fh 00040h 0003fh 0d600h 0d5ffh 00000h ffeffh ffe80h ffe7fh ffe39h ffe06h ffd00h ffcffh fd600h fffffh 10000h 0ffffh 0ffdfh 0ffd0h 0ff00h 0feffh 3ffffh 40000h 3ffffh 10000h 0d5ffh (256 bytes) special function register (sfr) internal rom (54784 bytes) internal ram (10496 bytes ) external memory note 1 (768 kb) note 1 general-purpose register (128 bytes) macro service control word area (42 bytes) data area (512 bytes) program/data area (9984 bytes) note 2 callf entry area (2 kb) program/data area note 3 callt table area (64 bytes) vector table area (64 bytes) internal ram (10496 bytes) external memory note 1 (775680 bytes) (256 bytes) special function register (sfr) internal rom (256 kb) when location 0h instruction is executed note 1 when location 0fh instruction is executed internal rom (196608 bytes)
27 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a 7.2 cpu registers 7.2.1 general-purpose registers sixteen 8-bit general-purpose registers are available. two 8-bit general-purpose registers can be used in com- bination as a 16-bit general-purpose register. four of the 16-bit registers can be used in combination with an 8-bit register for address extension as 24-bit address specification registers. eight banks of register sets are available, which can be selected by software or using the context switching function. the general-purpose registers, except registers v, u, t, and w for address extension, are mapped to the internal ram. figure 7-5. general-purpose register format caution r4, r5, r6, r7, rp2, and rp3 can be used as x, a, c, b, ax, and bc registers, respectively, by setting the rss bit of psw to 1. however, use this function only when using a program written for the 78k/iii series. a (r1) b (r3) r5 r7 r9 r11 d (r13) h (r15) v u t w vvp (rg4) uup (rg5) tde (rg6) whl (rg7) c (r2) r6 r8 r10 e (r12) l (r14) ax (rp0) rp2 rp3 vp (rp4) up (rp5) de (rp6) hl (rp7) ( ): absolute name 8 banks bc (rp1) r4 x (r0)
pd784935a,784936a,784937a,784938a 28 data sheet u13572ej2v0ds 7.2.2 control registers (1) program counter (pc) the contents of this 20-bit counter are automatically updated as a program is executed. figure 7-6. format of program counter (pc) (2) program status word (psw) this register holds the status of the cpu. its contents are automatically updated as a program is executed. figure 7-7. format of program status word (psw) note this flag is used to maintain compatibility with the 78k/iii series. keep this flag cleared to 0 except when using the software written for the 78k/iii series. (3) stack pointer (sp) this is a 24-bit pointer that holds the first address of the stack. be sure to write 0 to the higher 4 bits of this pointer. figure 7-8. format of stack pointer (sp) 19 0 pc 15 14 13 12 11 10 9 8 uf rbs2 rbs1 rbs0 pswh 76543210 s z rss note ac ie p/v 0 cy pswl psw 23 0 sp 20 0 0 0 0
29 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a 7.2.3 special function registers (sfrs) the special function registers (sfrs) are registers having a special function, such as the mode registers and control registers of the on-chip peripheral hardware, and are mapped to a 256-byte space of addresses 0ff00h to 0ffffh note . note this is the case when the location 0h instruction is executed. they are mapped to fff00h to fffffh when the location 0fh instruction is executed. caution do not access an address in this area to which no sfr is allocated. if such an address is accessed by mistake, the pd784938a may be deadlocked. the deadlock status can be released only by a reset. table 7-1 lists the special function registers (sfrs). the meanings of the symbols in this table are as follows: abbreviation .......................... abbre viation of the sfr. this abbreviation is reserved for use with nec s assem- bler (ra78k4). with the c compiler (cc78k4), this abbreviation can be used as an sfr variable when the #pragma sfr command is used. r/w ....................................... indicates whether the sfr can be read or written. r/w: read/write r: read only w: write only bit units for manipulation ..... indicates the bit units in which the sfr can be manipulated. an sfr that can be manipulated in 16-bit units can be written as operand sfrp. when specifying the sfr using an address, use the even address. an sfr that can be manipulated in 1-bit units can be written with a bit manipulation instruction. after reset ............................ indicates the status of the register when the reset signal is input.
pd784935a,784936a,784937a,784938a 30 data sheet u13572ej2v0ds table 7-1. special function register (sfr) list (1/4) address note special function register (sfr) name abbreviation r/w bit units for manipulation after reset 1 bit 8 bits 16 bits 0ff00h port 0 p0 r/w ? undefined 0ff01h port 1 p1 ? 0ff02h port 2 p2 r ? 0ff03h port 3 p3 r/w ? 0ff04h port 4 p4 ? 0ff05h port 5 p5 ? 0ff06h port 6 p6 ? 00h 0ff07h port 7 p7 ? undefined 0ff09h port 9 p9 ? 0ff0ah port 10 p10 ? 0ff0eh port 0 buffer register l p0l ? 0ff0fh port 0 buffer register h p0h ? 0ff10h compare register (timer/counter 0) cr00 0ff12h capture/compare register (timer/counter 0) cr01 0ff14h compare register l (timer/counter 1) cr10 cr10w ? 0ff15h compare register h (timer/counter 1) 0ff16h capture/compare register l (timer/counter 1) cr11 cr11w ? 0ff17h capture/compare register h (timer/counter 1) 0ff18h compare register l (timer/counter 2) cr20 cr20w ? 0ff19h compare register h (timer/counter 2) 0ff1ah capture/compare register l (timer/counter 2) cr21 cr21w ? 0ff1bh capture/compare register h (timer/counter 2) 0ff1ch compare register l (timer 3) cr30 cr30w ? 0ff1dh compare register h (timer 3) 0ff20h port 0 mode register pm0 ? ffh 0ff21h port 1 mode register pm1 ? 0ff23h port 3 mode register pm3 ? 0ff24h port 4 mode register pm4 ? 0ff25h port 5 mode register pm5 ? 0ff26h port 6 mode register pm6 ? 0ff27h port 7 mode register pm7 ? 0ff29h port 9 mode register pm9 ? 0ff2ah port 10 mode register pm10 ? 0ff2eh real-time output port control register rtpc ? 00h 0ff30h capture/compare control register 0 crc0 10h 0ff31h timer output control register toc ? 00h 0ff32h capture/compare control register 1 crc1 0ff33h capture/compare control register 2 crc2 10h note this is the case when the location 0h instruction is executed. when the location 0fh instruction is executed, f0000h is added to this value.
31 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a table 7-1. special function register (sfr) list (2/4) address note special function register (sfr) name abbreviation r/w bit units for manipulation after reset 1 bit 8 bits 16 bits 0ff36h capture register (timer/counter 0) cr02 r 0000h 0ff38h capture register l (timer/counter 1) cr12 cr12w ? 0ff39h capture register h (timer/counter 1) 0ff3ah capture register l (timer/counter 2) cr22 cr22w ? 0ff3bh capture register h (timer/counter 2) 0ff41h port 1 mode control register pmc1 r/w ? 00h 0ff43h port 3 mode control register pmc3 ? 0ff4ah port 10 mode control register pmc10 ? 0ff4eh pull-up resistor option register l puol ? 0ff4fh pull-up resistor option register h puoh ? 0ff50h timer register 0 tm0 r 0000h 0ff51h 0ff52h timer register 1 tm1 tm1w ? 0ff53h 0ff54h timer register 2 tm2 tm2w ? 0ff55h 0ff56h timer register 3 tm3 tm3w ? 0ff57h 0ff5ch prescaler mode register 0 prm0 r/w 11h 0ff5dh timer control register 0 tmc0 ? 00h 0ff5eh prescaler mode register 1 prm1 11h 0ff5fh timer control register 1 tmc1 ? 00h 0ff68h a/d converter mode register adm ? 00h 0ff6ah a/d conversion result register adcr r undefined 0ff6ch a/d current cut select register iead r/w ? 00h 0ff6fh watch timer mode register wm ? 0ff70h pwm control register pwmc ? 05h 0ff71h pwm prescaler register pwpr 00h 0ff72h pwm modulo register 0 pwm0 undefined 0ff74h pwm modulo register 1 pwm1 0ff78h rom correction control register corc ? 00h 0ff79h rom correction address pointer h corah 0ff7ah rom correction address pointer l coral 0000h 0ff7dh one-shot pulse output control register ospc ? 00h 0ff80h clocked serial interface mode register 3 csim3 ? 0ff82h clocked serial interface mode register csim ? 0ff84h clocked serial interface mode register 1 csim1 ? 0ff85h clocked serial interface mode register 2 csim2 ? 0ff86h serial shift register sio undefined note this is the case when the location 0h instruction is executed. when the location 0fh instruction is executed, f0000h is added to this value.
pd784935a,784936a,784937a,784938a 32 data sheet u13572ej2v0ds table 7-1. special function register (sfr) list (3/4) address note 1 special function register (sfr) name abbreviation r/w bit units for manipulation after reset 1 bit 8 bits 16 bits 0ff88h asynchronous serial interface mode register asim r/w ? 00h 0ff89h asynchronous serial interface mode register 2 asim2 ? 0ff8ah asynchronous serial interface status register asis r ? 0ff8bh asynchronous serial interface status register 2 asis2 ? 0ff8ch serial receive buffer: uart0 rxb undefined serial transmit shift register: uart0 txs w serial shift register: ioe1 sio1 r/w 0ff8dh serial receive buffer: uart2 rxb2 r serial transmit shift register: uart2 txs2 w serial shift register: ioe2 sio2 r/w 0ff8eh serial shift register 3: ioe3 sio3 0ff90h baud rate generator control register brgc 00h 0ff91h baud rate generator control register 2 brgc2 0ffa0h external interrupt mode register 0 intm0 ? 0ffa1h external interrupt mode register 1 intm1 ? 0ffa4h sampling clock select register scs0 0ffa8h in-service priority register ispr r ? 0ffaah interrupt mode control register imc r/w ? 80h 0ffach interrupt mask register 0l mk0l mk0 ?? ffffh 0ffadh interrupt mask register 0h mk0h ? 0ffaeh interrupt mask register 1l mk1l mk1 ?? 0ffafh interrupt mask register 1h mk1h ? 0ffb0h bus control register bcr ? 00h 0ffb2h unit address register uar 0000h 0ffb4h slave address register sar 0ffb6h partner address register par r 0ffb8h control data register cdr r/w 01h 0ffb9h message length register dlr 0ffbah data register dr 00h 0ffbbh unit status register usr r ? 0ffbch interrupt status register isr r/w ? 0ffbdh slave status register ssr r ? 41h 0ffbeh success count register scr 01h 0ffbfh communication count register ccr 20h 0ffc0h standby control register stbc r/w note 2 30h 0ffc2h watchdog timer mode register wdm note 2 00h notes 1. this is the case when the location 0h instruction is executed. when the location 0fh instruction is executed, f0000h is added to this value. 2. data can be written to these registers only by using dedicated instructions mov stbc, #byte and mov mdm, #byte. other instructions cannot be used.
33 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a table 7-1. special function register (sfr) list (4/4) address note 1 special function register (sfr) name abbreviation r/w bit units for manipulation after reset 1 bit 8 bits 16 bits 0ffc4h memory expansion mode register mm r/w ? 20h 0ffc5h hold mode register hldm ? 00h 0ffc6h clock output mode register clom ? 0ffc7h programmable wait control register 1 pwc1 aah 0ffc8h programmable wait control register 2 pwc2 aaaah 0ffcch refresh mode register rfm ? 00h 0ffcdh refresh area specification register rfa ? 0ffcfh oscillation stabilization time specification register osts 0ffd0h- external sfr area ? 0ffdfh 0ffe0h interrupt control register (intp0) pic0 ? 43h 0ffe1h interrupt control register (intp1) pic1 ? 0ffe2h interrupt control register (intp2) pic2 ? 0ffe3h interrupt control register (intt3) pic3 ? 0ffe4h interrupt control register (intc00) cic00 ? 0ffe5h interrupt control register (intc01) cic01 ? 0ffe6h interrupt control register (intc10) cic10 ? 0ffe7h interrupt control register (intc11) cic11 ? 0ffe8h interrupt control register (intc20) cic20 ? 0ffe9h interrupt control register (intc21) cic21 ? 0ffeah interrupt control register (intc30) cic30 ? 0ffebh interrupt control register (intp4) pic4 ? 0ffech interrupt control register (intp5) pic5 ? 0ffedh interrupt control register (intad) adic ? 0ffeeh interrupt control register (intser) seric ? 0ffefh interrupt control register (intsr) sric ? interrupt control register (intcsi1) csiic1 ? 0fff0h interrupt control register (intst) stic ? 0fff1h interrupt control register (intcsi) csiic ? 0fff2h interrupt control register (intser2) seric2 ? 0fff3h interrupt control register (intsr2) sric2 ? interrupt control register (intcsi2) csiic2 ? 0fff4h interrupt control register (intst2) stic2 ? 0fff6h interrupt control register (intie1) ieic1 ? 0fff7h interrupt control register (intie2) ieic2 ? 0fff8h interrupt control register (intw) wic ? 0fff9h interrupt control register (intcsi3) csiic3 ? 0fffch internal memory size switching register note 2 ims ffh notes 1. this is the case when the location 0h instruction is executed. when the location 0fh instruction is executed, f0000h is added to this value. 2. writing this register is meaningful only with the pd78f4938a.
pd784935a,784936a,784937a,784938a 34 data sheet u13572ej2v0ds 8. peripheral hardware functions 8.1 ports the ports shown in figure 8-1 are provided for various control operations. the function of each port is as shown in table 8-1. on-chip pull-up resistors can be specified for ports 0 to 6, 9, and 10 by means of software. figure 8-1. port configuration port 0 port 1 port 3 port 4 port 5 port 6 port 7 port 2 p00 p07 p10 p17 p20-p27 p30 p37 p40 p47 p50 p57 p60 p67 p70 p77 port 9 port 10 p90 p97 p100 p107 8
35 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a table 8-1. port functions port name pin name function software specification of pull-up resistor port 0 p00 to p07 input/output can be specified in 1-bit units. pull-up resistors can be specified for the can also operate as a 4-bit real-time output port (p00 pins in input mode all at once. to p03, p04 to p07). can drive a transistor. port 1 p10 to p17 input/output can be specified in 1-bit units. pull-up resistors can be specified for the can drive an led. pins in input mode all at once. port 2 p20 to p27 input port pull-up resistors can be specified in 6-bit units (p22 to p27). port 3 p30 to p37 input/output can be specified in 1-bit units. pull-up resistors can be specified for the p32/sck0 and p33/so0 pins can be used as n-ch pins in input mode all at once. open-drain pins. port 4 p40 to p47 input/output can be specified in 1-bit units. pull-up resistors can be specified for the can drive an led. pins in input mode all at once. port 5 p50 to p57 input/output can be specified in 1-bit units. pull-up resistors can be specified for the can drive an led. pins in input mode all at once. port 6 p60 to p67 input/output can be specified in 1-bit units. pull-up resistors can be specified for the pins in input mode all at once. port 7 p70 to p77 input/output can be specified in 1-bit units. port 9 p90 to p97 input/output can be specified in 1-bit units. pull-up resistors can be specified for the pins in input mode all at once. port 10 p100 to input/output can be specified in 1-bit units. pull-up resistors can be specified for the p107 p105/sck3 pin and p107/so3 pin can be used as pins in input mode all at once. n-ch open-drain pins.
pd784935a,784936a,784937a,784938a 36 data sheet u13572ej2v0ds 8.2 clock generator this circuit generates a clock necessary for operation. it is also provided with a frequency divider. when high- speed operation is not necessary, the power consumption can be lowered by reducing the internal operating frequency. figure 8-2. block diagram of clock generator note be sure to set bit 7 of the standby control register (stbc) to 1 when using the main clock. remark f xx : oscillation frequency f clk : internal operating frequency x1 f xx f xx /8 f xx /4 f xx /2 x2 oscillator 1/2 1/2 1/2 selector selector stbc.4,5 stbc.7 clocked synchronous 3-wire serial i/o (csi) asynchronous serial i/o (uart/ioe) intp0 noise eliminator oscillation stabilization timer timer/counter f clk to each cpu peripheral circuit operation clock of iebus controller note intw interrupt signal watch clock main clock 1 0 watch timer note
37 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a figure 8-3. example of using oscillator crystal/ceramic oscillation caution when using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. pd784938a v ss x1 x2
pd784935a,784936a,784937a,784938a 38 data sheet u13572ej2v0ds the subsystem oscillator has a low amplification factor so as to lower the current consumption and is more susceptible to noise than the main system clock oscillator. when using the subsystem clock circuit, therefore, utmost care must be exercised in wiring the circuit. if the oscillator does not operate correctly, the microcontroller cannot operate correctly, either. consult the oscillator manufacturer if you need an oscillation frequency at high accuracy. figure 8-4. notes on connecting resonator cautions 1. keep the oscillator as close to the x1 and x2 (xt1 and xt2) pins as possible. 2. do not pass any other signal lines through the region indicated by the dotted line. x2 x1 v ss pd784938a
39 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a 8.3 real-time output port the real-time output port outputs the data stored in the buffer in synchronization with the match interrupt of timer/ counter 1 or an external interrupt. as a result, it can output pulses without jitter. therefore, this port is ideal for applications where different patterns are output at different intervals (such as open loop control of a stepper motor). the real-time output port consists mainly of port 0 and the port 0 buffer registers (p0h and p0l) as shown in figure 8-5. figure 8-5. block diagram of real-time output port internal bus 844 44 8 real-time output port control register (rtpc) output trigger control circuit intp0 (from external device) intc10 (from timer/counter 1) intc11 (from timer/counter 1) p0h p0l output latch (p0) p07 p00 buffer registers
pd784935a,784936a,784937a,784938a 40 data sheet u13572ej2v0ds 8.4 timers/counters three timer/event counters and one timer are provided. in addition, because seven interrupt requests are supported, the timer/counters and timer can be used as seven timer/counters. table 8-2. operations of timers/counters name timer/event timer/event timer/event timer 3 item counter 0 counter 1 counter 2 count width 8 bits ?? 16 bits ??? operation mode interval timer 2ch 2ch 2ch 1ch external event counter ?? one-shot timer function timer output 2ch 2ch toggle output pwm/ppg output one-shot pulse output note real-time output pulse width measurement 1 input 1 input 2 inputs number of interrupt requests 2221 note the one-shot pulse output function is used to make a pulse output level active by software and inactive by hardware (interrupt request signal). this function is different from the one-shot timer function of timer/event counter 2 in nature.
41 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a figure 8-6. block diagram of timers/counters remark ovf: overflow flag prescaler edge detection selector clear control timer counter 0 (tm0) compare register (cr00) compare register (cr01) capture register (cr02) pulse output control ovf software trigger match to0 to1 intc00 intc01 intp3 intp3 f xx /4 timer/event counter 0 prescaler edge detection clear control compare register (cr10/cr10w) capture/compare register (cr11/cr11w) capture register (cr12/cr12w) ovf match match intc10 intc11 intp0 intp0 f xx /4 timer/event counter 1 timer counter 1 (tm1/tm1w) to real-time output port prescaler edge detection clear control timer counter 2 (tm2/tm2w) compare register (cr20/cr20w) capture/compare register (cr21/cr21w) capture register (cr22/cr22w) ovf to2 to3 intc20 intc21 intp1 intp1 f xx /4 timer/event counter 2 edge detection intp2 intp2/ci prescaler compare register (cr30/cr30w) uart, csi f xx /4 timer 3 timer counter 3 (tm3/tm3w) intc30 clear match selector selector pulse output control match match match event input
42 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a 8.5 watch timer the count clock to be input to the watch timer can be selected from the main clock (12.58 mhz) or watch clock (32.768 khz) by using a control register. the watch clock is input only to the watch timer and not to the cpu or other peripheral circuits. therefore, the operation speed of the cpu cannot be slowed down by the watch clock. the watch timer generates an interrupt signal (intw) at intervals of 0.5 seconds note by dividing the count clock. at the same time, it also sets an interrupt request flag (wif) (bit 7 of the interrupt control register (wic)). the interval of generating intw can be changed to about 1 ms by changing the mode (fast forward mode: 512 times faster than the normal mode). when the main clock is selected as the count clock, the watch timer stops its operation in the stop mode and idle mode. in the halt mode, however, it continues operating. when the watch clock is selected as the count clock, the watch timer can continue operating in any of the stop, idle, and halt modes. the operation of the watch clock oscillator is controlled by the watch timer mode register (wm). the watch timer of the pd784938a does not have a buzzer output function. note this doesn? mean the first intw occurs within 0.5 seconds after the operation has been enabled. table 8-3. relation between count clock and watch timer operation selection of count clock normal operation mode types of standby modes halt mode stop mode idle mode main clock can operate can operate stops stops watch clock can operate can operate can operate can operate the watch timer consists of a frequency divider that divides the count clock by three and a counter that divides the output of the frequency divider by 2 14 . as the count clock, select a signal resulting from dividing the internal system clock by 128 or the signal from the watch clock oscillator. figure 8-7. block diagram of watch timer 1234 10 11 12 13 14 56789 counter counter 1/3 divider sel sel sel wm.3 reset watch clock oscillator on/off wm.7 wm.6 wm.2 (set by instruction when main clock (12.58 mhz) is used) stbc.7 intw 1 0 0 1 0 1 main clock f xx /128
43 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a 8.6 pwm output (pwm0, pwm11) two pwm (pulse width modulation) output circuits with a resolution of 12 bits are provided. the active level of each pwm output channel can be selected independently of the other channel. the pwm output is ideal for controlling the speed of a dc motor. figure 8-8. block diagram of pwm output unit remark n = 0 or 1 internal bus 16 8 reload control 4 8 8-bit down counter prescaler pulse control circuit 4-bit counter output control 1/256 pwmn (output pin) pwm control register (pwmc) 0 3 4 7 8 15 pwmn (modulo register) f clk
44 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a 8.7 a/d converter an analog-to-digital (a/d) converter having 8 multiplexed analog input lines (ani0 to ani7) is provided. this a/d converter is of the successive approximation type, and the result of conversion is stored in an 8-bit a/d conversion result register (adcr). therefore, conversion can be carried out with a high accuracy. the a/d conversion operation can be started in the following two modes: hardware start: conversion is started by trigger input (intp5). software start: conversion is started by setting a bit of the a/d converter mode register (adm). after the conversion has been started, the following two operation modes can be selected. scan mode: two or more analog input pins are sequentially selected to convert multiple signals. select mode: only one analog input pin is used to successively convert one signal. these operations modes are selected and conversion is stopped by adm. when the result of conversion is transferred to adcr, the interrupt request intad is generated. by using this interrupt and a macro service, the converted values can be successively transferred to memory. cautions 1. apply the same voltage as the supply voltage (av dd ) to the reference voltage input pin (av ref1 ) of this product. 2. when port 7 is used both as an output port and a/d input lines, do not manipulate the output port while a/d conversion is in progress. figure 8-9. block diagram of a/d converter internal bus ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 intp5 input selector edge detector conversion trigger sample & hold circuit voltage comparator successive approximation register (sar) control circuit intad 8 series resistor string r/2 tap selector r r/2 av ref1 av dd av ss 8 trigger enable a/d converter mode register (adm) 8 a/d conversion result register (adcr) connection control a/d current cut select register (iead)
45 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a 8.8 serial interface four independent serial interface channels are provided. asynchronous serial interface (uart)/3-wire serial i/o (ioe) 2 clocked serial interface (csi) 2 3-wire serial i/o (ioe) therefore, communication with an external device and internal, local communication within the system can be performed simultaneously (refer to figure 8-10 ). figure 8-10. example of serial interface uart + 3-wire serial i/o + 2-wire serial i/o note handshake line pd4711a rs-232-c driver/ receiver [uart] [3-wire serial i/o] note si so sck port int port rxd txd v dd v dd so1 si1 sck1 intpm note sb0 sck0 port int si0 so0 sck0 intpn pd784938a (master) port port slave slave [2-wire serial i/o]
46 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a 8.8.1 asynchronous serial interface/3-wire serial i/o (uart/ioe) two serial interface channels that can select an asynchronous serial interface mode and 3-wire serial i/o mode are available. (1) asynchronous serial interface mode in this mode, 1-byte data is transmitted or received after a start bit. because an internal baud rate generator is available, communication can be performed at a wide range of baud rates. in addition, the baud rate can be defined by dividing the clock input to the asck pin. when the baud generator is used, a midi standard baud rate (31.25 kbps) can be also obtained. figure 8-11. block diagram in asynchronous serial interface mode remark f xx : oscillation frequency n = 0 to 11 m = 16 to 30 1/2m 1/2m 1/2 n+1 receive buffer rxb, rxb2 receive shift register transmit shift register receive control parity check transmit control parity append r x d, r x d2 t x d, t x d2 intsr, intsr2 intser, intser2 txs, txs2 intst, intst2 baud rate generator f xx asck, asck2 selector internal bus
47 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a (2) 3-wire serial i/o mode in this mode, the master device makes the serial clock active and starts transmission. one byte of data is communicated in synchronization with this clock. this interface mode is to communicate with a device with a conventional clocked serial interface. basically, communication is established by using three lines: serial clock (sck) and serial data (si and so). generally, a handshake line is necessary for checking the communication status. figure 8-12. block diagram in 3-wire serial i/o mode remark f xx : oscillation frequency n = 0 to 11 m = 1, or 16 to 30 internal bus direction control circuit sio1, sio2 shift register output latch serial clock counter interrupt generator 1/m 1/2 n+1 intcsi1, intcsi2 si1, si2 so1, so2 sck1, sck2 f xx selector serial clock control circuit
48 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a 8.8.2 clocked serial interface (csi) in this mode, the master device makes the serial clock active and starts transmission. one byte of data is communicated in synchronization with this clock. figure 8-13. block diagram of clocked serial interface remark f xx : oscillation frequency n = 0 or 3 son sin sckn internal bus sion register csimn register serial clock counter intcsin selector selector f xx /8 f xx /16 f xx /32 f xx /64 f xx /128
49 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a 3-wire serial i/o mode this mode is used to communicate with a device having a conventional clocked serial interface. basically, communication is performed by using three lines: serial clock (sckn) and serial data (sin and son) (n = 0 or 3). generally, a handshake line is necessary for checking the communication status. 8.9 clock output function the operating clock of the cpu can be divided and output to an external device. the line that outputs the divided clock can be also used as a 1-bit port. when this function is used, the local bus interface cannot be used, because the astb and clkout pins are multiplexed. figure 8-14. block diagram of clock output function clkout output control output enable output level f clk f clk /2 f clk /4 f clk /8 f clk /16 selector
50 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a 8.10 edge detection function the interrupt input pins (nmi and intp0 to intp5) are used to input trigger signals for the on-chip hardware units, as well as to input interrupt requests. because these pins operate at the edge of an input signal, they are provided with a function to detect edges. in addition, these pins also have a noise eliminator function to prevent erroneous detection of an edge due to noise. table 8-4. noise elimination of interrupt input pins pin name detectable edge noise rejection nmi either rising or falling edge by analog delay intp0 to intp3 either or both rising or falling edge by clock sampling note intp4, intp5 by analog delay note intp0 can select a sampling clock. 8.11 watchdog timer a watchdog timer is provided to detect inadvertent program loop of the cpu. this watchdog timer generates a non- maskable interrupt request unless it is cleared by software within specified interval time. once the watchdog timer has been enabled to operate, it cannot be stopped by software. it can be specified whether the interrupt request from the watchdog timer or the interrupt request from the nmi pin takes precedence. figure 8-15. block diagram of watchdog timer selector f clk /2 21 f clk /2 20 f clk /2 19 f clk /2 17 f clk clear signal timer intwdt
51 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a 8.12 simplified iebus controller the pd784938a has a newly developed iebus controller. the functions of this controller are limited compared with the iebus interface function (provided to the 78k/0 series) of conventional microcontrollers. table 8-5 compares the simplified iebus interface of the pd784938a and the conventional iebus interface. table 8-5. comparison between conventional iebus interface and simplified iebus interface item conventional model (iebus of 78k/0) simplified iebus communication mode mode 0, mode 1, mode 2 fixed to mode 1 internal system clock 6.0 (6.29) mhz internal buffer size transmit buffer: 33 bytes (fifo) transmit/receive register: 1 byte receive buffer: 40 bytes (fifo) up to 4 frames can be received. cpu processing preprocessing before start of communication preprocessing before start of communication (data setting) (data setting) setting and managing each communication status setting and managing each communication status data write to transmit buffer 1-byte data write processing data read from receive buffer 1-byte data read processing management of transmission such as slave status multiple frame management, re-master request processing hardware processing bit processing (modulation/demodulation, error bit processing (modulation/demodulation, error detection) detection) field processing (generation/management) field processing (generation/management) arbitration result detection arbitration result detection parity processing (generation/error detection) parity processing (generation/error detection) automatic returning of ack/nack automatic returning of ack/nack automatic data re-transmission processing automatic data re-transmission processing automatic re-master processing automatic transmission processing such as slave status multiple frame reception processing
52 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a figure 8-16. block diagram of iebus controller bcr(8) uar ( 12 ) sar ( 12 ) par ( 12 ) cdr ( 8 ) dlr ( 8 ) dr ( 8 ) usr(8) isr ( 8 ) ssr(8) scr(8) ccr(8) 8121212888 8 12 12 8 8 8 888 888 88 8 12 nf rx tx mpx mpx 12-bit latch comparator conflict detection ack generation parity generation error detection tx/rx interrupt control circuit interrupt control block int request (vector, macro service) cpu interface block internal registers iebus interface block clk bit processing block field processing block internal bus r/w psr(8 bits) internal bus 8 8 5 12 8
53 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a hardware configuration and function the iebus internally consists of the following six blocks: cpu interface block interrupt control block internal registers bit processing block field processing block iebus interface block this control block interfaces the cpu (78k/iv) with the iebus. this block passes interrupt request signals from the iebus to the cpu. these registers specify the data in each field of the control register that controls the iebus. this block generates and disassembles bit timing, and mainly consists of a bit sequence rom, 8-bit preset timer, and decision unit. this block generates each field in a communication frame, and mainly consists of a field sequence rom, 4-bit down counter, and decision unit. this block is used to interface with an external driver/receiver, and mainly consists of a noise filter, shift register, conflict detection unit, parity detection unit, parity generator, and ack/nack generator.
54 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a 9. interrupt function to service an interrupt, the three servicing formats shown in table 9-1 can be selected in software. table 9-1. interrupt request servicing servicing mode main body of servicing contents of pc and psw servicing routine vectored interrupt software branches to and executes servicing routine saves to and restores (any servicing). from stack. context switching automatically selects register bank, and branches to saves to or restores from and executes servicing routine (any servicing). fixed area in register bank. macro service firmware executes data transfer between memory and i/o held (servicing is fixed). 9.1 interrupt sources the sources of interrupts include the 27 sources listed in table 9-2, execution of the brk or brkcs instruction, and operand errors. four interrupt priority levels can be selected, so that nesting of interrupts can be controlled and that two or more interrupt requests that are simultaneously generated can be controlled. when a macro service is used, however, nesting always progresses (is not kept pending). the default priority determines the priorities of the servicing of two or more interrupt requests that are generated at the same time (fixed priorities) (refer to table 9-2 ).
55 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a table 9-2. interrupt sources type default source internal/ macro priority name tr igger external service software brk execution of instruction instruction brkcs execution of instruction instruction operand if result of exclusive-or of operands byte and byte is not ffh when error mov stbc, #byte, mov wdm, #byte, or location instruction is executed non- nmi detection of pin input edge external maskable wdt overflow of watchdog timer internal maskable 0 (highest) intp0 detection of pin input edge (tm1/tm1w capture trigger) external 1 intp1 detection of pin input edge (tm2/tm2w capture trigger) 2 intp2 detection of pin input edge (tm2/tm2w event counter input) 3 intp3 detection of pin input edge (tm0 capture trigger) 4 intc00 generation of tm0 to cr00 matching signal internal 5 intc01 generation of tm0 to cr01 matching signal 6 intc10 generation of tm1 to cr10 matching signal (in 8-bit operation mode) generation of tm1w to cr10w matching signal (in 16-bit operation mode) 7 intc11 generation of tm1 to cr11 matching signal (in 8-bit operation mode) generation of tm1w to cr11w matching signal (in 16-bit operation mode) 8 intc20 generation of tm2 to cr20 matching signal (in 8-bit operation mode) generation of tm2w to cr20w matching signal (in 16-bit operation mode) 9 intc21 generation of tm2 to cr21 matching signal (in 8-bit operation mode) generation of tm2w to cr21w matching signal (in 16-bit operation mode) 10 intc30 generation of tm3 to cr30 matching signal (in 8-bit operation mode) generation of tm3w to cr30w matching signal (in 16-bit operation mode) 11 intp4 detection of pin input edge external 12 intp5 detection of pin input edge 13 intad end of a/d conversion (transfer of adcr) internal 14 intser occurrence of asi0 reception error 15 intsr end of asi0 reception or end of csi1 transfer intcsi1 16 intst end of asi0 transmission 17 intcsi end of csi0 transfer 18 intser2 occurrence of asi2 reception error 19 intsr2 end of asi2 reception or end of csi2 transfer intcsi2 20 intst2 end of asi2 transmission 21 intie1 iebus data access request 22 intie2 occurrence of iebus communication error and start/end of communication 23 intw watch timer output 24 (lowest) intcsi3 end of csi3 transfer remark asi : asynchronous serial interface csi : clocked serial interface
56 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a 9.2 vectored interrupt if an interrupt occurs, execution branches to the interrupt routine, using the contents of the vector table address corresponding to the interrupt source as the branch destination address. the following operations are performed so that the cpu executes interrupt servicing. when execution branches: saves the status of the cpu (contents of pc and psw) to stack when execution returns: restores the status of the cpu (contents of pc and psw) from stack to return execution from an interrupt routine to the main routine, the reti instruction is used. the branch destination address must be in the range 0 to ffffh. table 9-3. vector table address interrupt source vector table address brk instruction 003eh operand error 003ch nmi 0002h wdt 0004h intp0 0006h intp1 0008h intp2 000ah intp3 000ch intc00 000eh intc01 0010h intc10 0012h intc11 0014h intc20 0016h intc21 0018h intc30 001ah intp4 001ch intp5 001eh intad 0020h intser 0022h intsr 0024h intcsi1 intst 0026h intcsi 0028h intser2 002ah intsr2 002ch intcsi2 intst2 002eh interrupt source vector table address intie1 0032h intie2 0034h intw 0036h intcsi3 0038h
57 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a 9.3 context switching context switching is a function used to select a specific register bank by hardware when an interrupt request is generated or when the brkcs instruction is executed. program execution then branches to the vector address stored in advance in the register bank and, at the same time, the current contents of the program counter (pc) and program status word (psw) are temporarily stored in the register bank. the branch destination address is in the range 0 to ffffh. figure 9-1. context switching operation when an interrupt request is generated 9.4 macro service a macro service is a function used to transfer data between memory and a special function register (sfr) without the intervention of the cpu. a macro service controller accesses memory and sfr in the same transfer cycle, and directly transfers data without loading it. because it is not necessary to save or restore the status of the cpu or to load data, data can be transferred at high speed using this function. figure 9-2. macro service cpu memory sfr macro service controller read write write read internal bus register bank n (n = 0 to 7) 0000b <7> transfer pc19-16 pc15-0 <6> exchange <5> save <2> save (bits 8 to 11 of temporary register) temporary register <1> save psw v u t w a b r5 r7 d h x c r4 r6 e l vp up <3> register bank selection (rbs0-rbs2 n) <4> rss 0 ie 0 register bank (0 to 7)
58 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a 9.5 application examples of macro service (1) transmit operation of serial interface each time a macro service request (intst) is generated, the next transmit data is transferred from memory to txs. when data n (last byte) is transferred to txs (when the transmit data storage buffer becomes empty), a vectored interrupt request (intst) is generated. (2) receive operation of serial interface each time a macro service request (intsr) is generated, the receive data is transferred from rxb to memory. when data n (last byte) is transferred to memory (when no more vacant area is available in the receive data storage buffer), a vectored interrupt request (intsr) is generated. transmit data storage buffer (memory) data n data n 1 data 1 data 2 internal bus transmit shift register txs(sfr) transmission control intst txd receive data storage buffer (memory) data n data n 1 data 1 data 2 internal bus receive shift register rxb(sfr) reception control intsr rxd receive buffer
59 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a (3) real-time output port intc10 and intc11 are used as the output triggers of the real-time output port. the macro service corre- sponding to these interrupts can set the next output pattern and interval at the same time. therefore, intc10 and intc11 can control two stepper motors independently. the real-time output port can be also used to control pwm and a dc motor. each time a macro service request (intc10) is generated, the pattern and timing are transferred to a buffer register (p0l) and a compare register (cr10), respectively. if the contents of the timer register 1 (tm1) coincide with those of cr10, the next intc10 is generated, and at the same time, the contents of p0l are sent to the output latch. when tn (last byte) is transferred, a vectored interrupt request (intc10) is generated. the same applies to intc11. t n t n 1 t 1 t 2 internal bus cr10 (sfr) tm1 intc10 output pattern profile (memory) p n p n 1 p 1 p 2 internal bus p0l output latch (sfr) match p00-p03 output timing profile (memory)
60 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a 10. local bus interface the local bus interface is used to connect an external memory or i/o (memory mapped i/o), supporting a memory space of 1 mb (refer to figure 10-1 ). figure 10-1. example of local bus interface 10.1 memory expansion the memory space can be expanded in seven steps, from 256 bytes to 1 mb, by connecting an external program memory or data memory. decoder latch pseudo sram prom pd27c1001a kanji character generator pd24c1000 data bus address bus gate array i/o extension centronics i/f, etc. pd784938a a16-a19 rd wr refrq ad0-ad7 astb a8-a15
61 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a 10.2 memory space the 1 mb memory space is divided into eight areas by logical addresses. each of these areas can be controlled by using the programmable wait function and pseudo static ram refresh function. figure 10-2. memory space fffffh 80000h 7ffffh 40000h 3ffffh 20000h 1ffffh 10000h 0ffffh 0c000h 0bfffh 08000h 07fffh 04000h 03fffh 00000h 512 kb 256 kb 128 kb 64 kb 16 kb 16 kb 16 kb 16 kb
62 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a 10.3 programmable wait the memory space can be divided into eight areas. wait cycles can be inserted while the rd and wr signals are active for each of these areas independently. therefore, even when memory with a different access times is con- nected, the efficiency of the entire system does not drop. in addition, an address wait function that extends the active period of the astb signal to ensure the lapse of address decode time is also available (this function can be used on the entire memory space). 10.4 pseudo static ram refresh function the refresh operations include the following operations: pulse refresh a bus cycle that outputs a refresh pulse to the refrq pin is inserted at specific intervals. the memory is divided into eight areas. when a specified area is accessed, the refresh pulse can be output from the refrq pin, so that the ordinary memory access is not kept waiting by the refresh cycle. power-down self-refresh the contents of the pseudo static ram are retained by outputting a low level to the refrq pin in the standby mode. 10.5 bus hold function the bus hold function facilitates connection of a dma controller. when a bus hold request signal (hldrq) is received from an external bus master, and once the bus cycle under execution is completed, the address bus, address/ data bus, and astb, rd, and wr pins go into a high-impedance state. the bus hold acknowledge signal (hldak) is made active, and the bus is released to the external bus master. when the bus hold function is used, the external wait function and pseudo static ram refresh function cannot be used.
63 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a 11. standby function the standby function is used to reduce the power consumption of the chip and can be used in the following modes: halt mode: in this mode, the operation clock of the cpu is stopped. this mode can reduce the average power consumption when used in combination with the normal operation mode for intermittent operation. idle mode: in this mode, the operation of the oscillator continues but the other circuits of the system are stopped. the power consumption in this mode is close to that in the stop mode, but the time required for the program execution to restore to the normal status from this mode is equivalent to the time in the halt mode. stop mode: in this mode, the oscillator is stopped. all the operations of the chip are stopped, so that the power consumption is minimized with only leakage current flowing. these modes are programmable. a macro service can be started from the halt mode. figure 11-1. status transition in standby mode notes 1. when intw, intp4, and intp5 are not masked 2. only interrupt requests that are not masked 3. subclock operation remark only an externally input nmi is valid. the watchdog timer cannot be used to release a standby mode (stop/halt/idle). waits for stabilization of oscillation program operation macro service halt (standby) idle (standby) stop (standby) end of oscillation stabilization time macro service request end of one processing end of macro service macro service request end of one processing interrupt request note 2 reset input halt setting masked interrupt request idle setting reset input intw notes 1, 3, nmi, intp4, intp5 input note 1 stop setting reset input intw notes 1, 3, nmi, intp4, intp5 input note 1
64 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a 12. reset function when a low level is input to the reset pin, the internal hardware is initialized (reset status). when the reset pin goes high, the following data is written to the program counter (pc): lower 8 bits of pc: contents of address 0000h middle 8 bits of pc: contents of address 0001h higher 4 bits of pc: 0 the contents of the pc are used as a branch destination address, and program execution is started from that address. therefore, execution can be reset and started from any address. set the contents of each register in software as necessary. the reset input circuit has a noise eliminator to prevent malfunctioning due to noise. this noise eliminator is a sampling circuit using analog delay. figure 12-1. reception of reset signal keep the reset signal active until the oscillation stabilization time (about 40 ms) has elapsed when the reset operation is performed on power application. figure 12-2. reset operation on power application delay reset (input) delay internal reset signal reset starts reset ends delay pc initialization execution of instruction at reset start address reset (input) internal reset signal reset ends oscillation stabilization time delay pc initialization execution of instruction at reset start address v dd
65 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a 13. regulator the pd784938a has a regulator (circuit that helps the internal circuitry operate at a low voltage) to reduce the power consumption of the device. the operation of this regulator is controlled by the input level of the regoff pin. when the regoff pin goes high, the regulator is turned off; when it goes low, the regulator is turned on. when the regulator is on, operation at a low voltage become possible. in the pd784938a, operation with the regulator turned on (regoff pin = low level) is recommended. to stabilize the output voltage of the regulator, connect a capacitor of 1 f to the regc pin (regulator stabilization capacitor connecting pin). when the regulator is stopped, apply the same level as v dd to the regc pin. figure 13-1 shows the peripheral circuits of the regulator. figure 13-1. block diagram of regulator peripheral processing of regc pin when regulator operates connect capacitor (1 f) to stabilize regulator. when regulator stops supply v dd . regoff v dd regc regulator low level: high level: internal supply voltage (supply to cpu and each peripheral circuit) regulator on regulator off 1 f
66 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a 14. rom correction rom correction is a function to replace part of a program in the internal rom with a program in the internal ram for execution. by using this function, bugs found in the internal rom can be avoided or the program flow can be changed. rom correction can be used at up to four places in the internal rom (program). figure 14-1. block diagram of rom correction function remark n = 0 to 3, m = 0 or 1 program counter (pc) comparator corenn correction address pointer n correction address registers (corah, coral) corchm rom correction control register (corc) coincidence internal bus correction branch processing request signal (callt instruction)
67 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a 15. instruction set (1) 8-bit instructions (( ) indicates a combination implemented by using a as r.) mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, shr, shl, sor4, rol4, dbnz, push, pop, movm, xchm, cmpme, cmpmne, cmpmnc, cmpmc, movbk, xchbk, cmpbke, cmpbkne, cmpbknc, cmpbkc table 15-1. 8-bit instructions and addressing second #byte a r saddr sfr !addr16 mem r3 [whl+] n none note 2 operand r saddr !!addr24 [saddrp] pswl [whl ] first operand [%saddrg] pswh a (mov) (mov) mov (mov) note 6 mov (mov) mov mov (mov) add note 1 (xch) xch (xch) note 6 (xch) (xch) xch (xch) (add) note 1 (add) note 1 (add) notes 1, 6 (add) note 1 add note 1 add note 1 (add) note 1 r mov (mov) mov mov mov mov ror note 3 mulu add note 1 (xch) xch xch xch xch divuw (add) note 1 add note 1 add note 1 add note 1 inc dec saddr mov (mov) note 6 mov mov inc add note 1 (add) note 1 add note 1 xch dec add note 1 dbnz sfr mov mov mov push add note 1 (add) note 1 add note 1 pop !addr16 mov (mov) mov !!addr24 add note 1 mem mov [saddrp] add note 1 [%saddrg] mem3 ror4 rol4 r3 mov mov pswl pswh b, c dbnz stbc, wdm mov [tde+] (mov) movbk note 5 [tde ] (add) note 1 movm note 4 notes 1. the operand of addc, sub, subc, and, or, xor, and cmp is the same as that of add. 2. either the second operand is not used or the second operand is not an operand address. 3. the operand of rol, rorc, rolc, shr, and shl is the same as that of ror. 4. the operand of xchm, cmpme, cmpmne, cmpmnc, and cmpmc is the same as that of movm. 5. the operand of xchbk, cmpbke, cmpbkne, cmpbknc, and cmpbkc is the same as that of movbk. 6. if saddr is saddr2 in this combination, the code length of some instructions is short.
68 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a (2) 16-bit instructions (( ) indicates a combination implemented by using ax as rp.) movw, xchw, addw, subw, cmpw, muluw, mulw, divux, incw, decw, shrw, shlw, push, pop, addwg, subwg, pushu, popu, movtblw, macw, macsw, sacw table 15-2. 16-bit instructions and addressing second #word ax rp saddrp sfrp !addr16 mem [whl+] byte n none note 2 operand rp saddrp !!addr24 [saddrp] first operand [%saddrg] ax (movw) (movw) (movw) (movw) note 3 movw (movw) movw (movw) addw note 1 (xchw) (xchw) (xchw) note 3 (xchw) xchw xchw (xchw) (add) note 1 (addw) note 1 (addw) notes 1, 3 (addw) note 1 rp movw (movw) movw movw movw movw shrw mulw note 4 addw note 1 (xchw) xchw xchw xchw shlw incw (addw) note 1 addw note 1 addw note 1 addw note 1 decw saddrp movw (movw) note 3 movw movw incw addw note 1 (addw) note 1 addw note 1 xchw decw addw note 1 sfrp movw movw movw push addw note 1 (addw) note 1 addw note 1 pop !addr16 movw (movw) movw movtblw !!addr24 mem movw [saddrp] [%saddrg] psw push pop sp addwg subwg post push pop pushu popu [tde+] (movw) sacw byte macw macsw notes 1. the operand of subw and cmpw is the same as that of addw. 2. either the second operand is not used or the second operand is not an operand address. 3. if saddrp is saddrp2 in this combination, the code length of some instructions is short. 4. the operand of muluw and divux is the same as that of mulw.
69 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a (3) 24-bit instructions (( ) indicates a combination implemented by using whl as rg.) movg, addg, subg, incg, decg, push, pop table 15-3. 24-bit instructions and addressing second #imm24 whl rg saddrg !!addr24 mem1 [%saddrg] sp none note 2 operand rg first operand whl (movg) (movg) (movg) (movg) (movg) movg movg movg (addg) (addg) (addg) addg (subg) (subg) (subg) subg rg movg (movg) movg movg movg incg addg (addg) addg decg subg (subg) subg push pop saddrg (movg) movg !!addr24 (movg) movg mem1 movg [%saddrg] movg sp movg movg incg decg note either the second operand is not used or the second operand is not an operand address.
70 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a (4) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr, bfset table 15-4. bit manipulation instructions and addressing second operand cy saddr.bit sfr.bit /saddr.bit /sfr.bit none note a.bit x.bit /a.bit /x.bit pswl.bit pswh.bit /pswl.bit /pswh.bit mem2.bit /mem2.bit first operand !addr16.bit !!addr24.bit /!addr16.bit /!!addr24.bit cy mov1 and1 not1 and1 or1 set1 or1 clr1 xor1 saddr.bit mov1 not1 sfr.bit set1 a.bit clr1 x.bit bf pswl.bit bt pswh.bit btclr mem2.bit bfset !addr16.bit !!addr24.bit note either the second operand is not used or the second operand is not an operand address.
71 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a (5) call/return instructions/branch instructions call, callf, callt, brk, ret, reti, retb, retcs, retcsb, brkcs, br, bnz, bne, bz, be, bnc, bnl, bc, bl, bnv, bpo, bv, bpe, bp, bn, blt, bge, ble, bgt, bnh, bh, bf, bt, btclr, bfset, dbnz table 15-5. call/return and branch instructions and addressing operand of $addr20 $!addr20 !addr16 !!addr20 rp rg [rp] [rg] !addr11 [addr5] rbn none note instruction address basic instruction bc note call call call call call call call callf callf brkcs brk br br br br br br br br ret retcs reti retcsb retb compound bf instruction bt btclr bfset dbnz note the operand of bnz, bne, bz, be, bnc, bnl, bl, bnv, bpo, bv, bpe, bp, bn, blt, bge, ble, bgt, bnh, and bh is the same as that of bc. (6) other instructions adjba, adjbs, cvtbw, location, sel, not, ei, di, swrs
72 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a 16. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd ?.3 to +6.5 v av dd ?.3 to v dd + 0.3 v av ss ?.3 to v ss + 0.3 v av ref1 a/d converter reference voltage input ?.3 to v dd + 0.3 v input voltage v i1 ?.3 to v dd + 0.3 v analog input voltage v ian analog input voltage av ss ?0.3 to av ref1 + 0.3 v output voltage v o ?.3 to v dd + 0.3 v output current, low i ol per pin 10 ma total of all pins of ports 0, 3, 6, 10 and the 50 ma p54 to p57 pins total of all pins of ports 1, 4, 7, 9, and the 50 ma p50 to p53, pwm0, pwm1, and tx pins output current, high i oh per pin ? ma total of all pins of ports 0, 3, 6, 10 and the ?0 ma p54 to p57 pins total of all pins of ports 1, 4, 7, 9, and the ?0 ma p50 to p53, pwm0, pwm1, and tx pins operating ambient temperature t a ?0 to +85 c storage temperature t stg ?5 to +150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
73 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a operating conditions clock frequency clock frequency supply voltage 2 mhz f xx 12.58 mhz 4.0 v dd 5.5 v 2 mhz f xx 6.29 mhz 3.0 v dd 5.5 v operating ambient temperature (t a ): 40 to +85 c power supply voltage and clock cycle time: refer to figure 16-1 selection of internal regulator operation (regoff pin: low-level input) figure 16-1. power supply voltage and clock cycle time capacitance (t a = 25 c, v dd = v ss = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c in f = 1 mhz 15 pf output capacitance c out unmeasured pins returned to 0 v. 15 pf i/o capacitance c io 15 pf guaranteed operating range 10000 4000 1000 500 200 159 100 79 0 0123 power supply voltage [v] clock cycle time t cyk [ns] 456 1/8 of f xx = 2 mhz f xx = 6.29 mhz undivided f xx = 12.58 mhz undivided
74 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a main oscillator characteristics (t a = ?0 to +85 c, v dd = 3.0 to 5.5 v, v ss = 0 v) parameter symbol conditions min. max. unit oscillator frequency f xx ceramic resonator or 4.0 v dd 5.5 v 2.0 12.58 mhz recommended resonator 3.0 v dd 5.5 v 2.0 6.29 mhz caution when using the main clock oscillator, wire as follows to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. remarks 1. connect a 12.582912 mhz or 6.291456 mhz oscillator to operate the internal clock timer with the main clock. 2. for the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. clock oscillator characteristics (t a = ?0 to +85 c, v dd = 3.0 to 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit oscillator frequency f xt ceramic resonator or crystal resonator 32 32.768 35 khz oscillation stabilization time f sxt 4.5 v dd 5.5 v 1.2 2 s 10 s oscillation hold voltage v ddxt 3.0 5.5 v watch timer operating voltage v ddw 3.0 5.5 v
75 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a dc characteristics (t a = ?0 to +85 c, v dd = av dd = 3.0 to 5.5 v, v ss = av ss = 0 v) (1/2) parameter symbol conditions min. typ. max. unit input voltage, low note v il1 p10, p11, p13 to p17, p30, p31, 0.3 0.3v dd v p34 to p37, p70 to p77, p90 to p97, p100 to p104, x1, x2, xt1, xt2 v il2 p12, p20 to p27, p32, p33, p105 to p107 0.3 0.2v dd v reset v il3 p00 to p07, p40 to p47, 4.5 v dd 5.5 v 0.3 0.8 v v il4 p50 to p57, p60 to p67 0.3 0.2v dd v input voltage, high v ih1 p10, p11, p13 to p17, p30, p31, 0.7v dd v dd +0.3 v p34 to p37, p70 to p77, p90 to p97, p100 to p104, x1, x2, xt1, xt2 v ih2 p12, p20 to p27, p32, p33, p105 to p107 0.8v dd v dd +0.3 v reset v ih3 p00 to p07, p40 to p47, 4.5 v dd 5.5 v 2.2 v dd +0.3 v v ih4 p50 to p57, p60 to p67 0.7v dd 0.3v dd v output voltage, low v ol1 i ol = 20 a 0.1 v i ol = 100 a 0.2 v i ol = 2 ma 0.4 v v ol2 i ol = 8 ma, p10 to p17, 4.5 v dd 5.5 v 1.0 v p40 to p47, p50 to p57 output voltage, high v oh1 i oh = 20 av dd 0.1 v i ol = 100 av dd 0.2 v i ol = 2 ma v dd 1.0 v v oh2 i ol = 5 ma, 4.5 v v dd 5.5 v v dd 2.4 v p10 to p17, p40 to p47, p50 to p57 input leakage current, low i lil1 v in = 0 v for pins other than 10 a x1, x2, xt1, and xt2 i lil2 x1, x2, xt1, xt2 20 a input leakage current, high i lih1 v in = v dd for pins other than 10 a x1, x2, xt1, and xt2 i lih2 x1, x2, xt1, xt2 20 a output leakage current, low i lol1 v out = 0 v 10 a output leakage current, high i loh1 v out = v dd 10 a note these values are valid when the pull-up resistor is off.
76 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a dc characteristics (t a = ?0 to +85 c, v dd = av dd = 3.0 to 5.5 v, v ss = av ss = 0 v) (2/2) parameter symbol conditions min. typ. max. unit power supply current i dd1 operating f xx = 12.58 mhz, 10 20 ma mode 4.0 v v dd 5.5 v f xx = 6.29 mhz, 5 10 ma 3.0 v v dd 5.5 v i dd2 halt mode f xx = 12.58 mhz, when 2 4 ma peripheral clock stops note , 4.0 v v dd 5.5 v f xx = 6.29 mhz, when 1.2 2.4 ma peripheral clock stops note , 3.0 v v dd 5.5 v i dd3 idle mode f xx = 12.58 mhz, 0.6 1.2 ma 4.0 v dd 5.5 v f xx = 6.29 mhz, 0.3 0.6 ma 3.0 v v dd 5.5 v data hold voltage v dddr stop mode 2.5 5.5 v data hold current i dddr stop mode v dd = 2.5 v, subclock stops 2 10 a v dd = 5.5 v, subclock stops 10 50 a pull-up resistor r l v in = 0 v 15 40 80 k ? note when the main system clock: f clk = f xx /8 is selected (set by the standby control register (stbc)) and the watch timer is operating. remark these values are valid when the internal regulator is on (regoff pin = low-level input).
77 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a ac characteristics (t a = ?0 to +85 c, v dd = av dd = 3.0 to 5.5 v, v ss = av ss = 0 v) (1) read/write operation (1/2) parameter symbol conditions min. typ. max. unit cycle time t cyk 4.0 v dd 5.5 v 79 ns v dd = 3.0 v 159 ns address setup time t sast v dd = 5.0 v (0.5+a) t 11 ns (to astb )v dd = 3.0 v (0.5+a) t 15 ns address hold time t hstla v dd = 5.0 v 0.5t 19 ns (from astb )v dd = 3.0 v 0.5t 24 ns astb high-level width t wsth v dd = 5.0 v (0.5+a) t 17 ns v dd = 3.0 v (0.5+a) t 40 ns address hold time (from rd )t hra v dd = 5.0 v 0.5t 14 ns v dd = 3.0 v 0.5t 14 ns delay from address to rd t dar v dd = 5.0 v (1+a) t 5ns v dd = 3.0 v (1+a) t 10 ns address float time (from rd )t far 0ns data input time from address t daid v dd = 5.0 v (2.5+a+n) t 37 ns v dd = 3.0 v (2.5+a+n) t 52 ns data input time from astb t dstid v dd = 5.0 v (2+n) t 35 ns v dd = 3.0 v (2+n) t 50 ns data input time from rd t drid v dd = 5.0 v (1.5+n) t 40 ns v dd = 3.0 v (1.5+n) t 50 ns delay from astb to rd t dstr v dd = 5.0 v 0.5t 9ns v dd = 3.0 v 0.5t 9ns data hold time (from rd )t hrid 0ns address active time from rd t dra v dd = 5.0 v 0.5t 2ns v dd = 3.0 v 0.5t 12 ns delay from rd to astb t drst v dd = 5.0 v 0.5t 9ns v dd = 3.0 v 0.5t 9ns rd low-level width t wrl v dd = 5.0 v (1.5+n) t 25 ns v dd = 3.0 v (1.5+n) t 30 ns remarks 1. t: t cyk = 1/f clk (f clk : internal system clock cycle) 2. a: 1 during address wait; otherwise 0 3. n: number of wait states (n 0) 4. calculated as t = 79 ns (min.) @ v dd = 5.0 v 5. calculated as t = 159 ns (min.) @ v dd = 3.0 v
78 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a ac characteristics (t a = ?0 to +85 c, v dd = av dd = 3.0 to 5.5 v, v ss = av ss = 0 v) (1) read/write operation (2/2) parameter symbol conditions min. typ. max. unit delay from address to wr t daw v dd = 5.0 v (1+a) t 5ns v dd = 3.0 v (1+a) t 10 ns address hold time (from wr )t hwa v dd = 5.0 v 0.5t 14 ns v dd = 3.0 v 0.5t 14 ns delay from astb to data t dstod v dd = 5.0 v 0.5t+15 ns output v dd = 3.0 v 0.5t+20 ns data output time from wr t dwod 15 ns delay from astb to wr t dstw v dd = 5.0 v 0.5t 9ns v dd = 3.0 v 0.5t 9ns data setup time (to wr )t sodwr v dd = 5.0 v (1.5+n) t 20 ns v dd = 3.0 v (1.5+n) t 25 ns data hold time (from wr )t hwod v dd = 5.0 v 0.5t 14 ns v dd = 3.0 v 0.5t 14 ns delay from wr to astb t dwst v dd = 5.0 v 0.5t 9ns v dd = 3.0 v 0.5t 9ns wr low-level width t wwl v dd = 5.0 v (1.5+n) t 25 ns v dd = 3.0 v (1.5+n) t 30 ns remarks 1. t: t cyk = 1/f clk (f clk : internal system clock cycle) 2. a: 1 during address wait; otherwise 0 3. n: number of wait states (n 0) 4. calculated as t = 79 ns (min.) @ v dd = 5.0 v 5. calculated as t = 159 ns (min.) @ v dd = 3.0 v
79 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a ac characteristics (t a = ?0 to +85 c, v dd = av dd = 3.0 to 5.5 v, v ss = av ss = 0 v) (2) external wait timing parameter symbol conditions min. typ. max. unit wait input time from t dawt v dd = 5.0 v (2+a) t 40 ns address v dd = 3.0 v (2+a) t 60 ns wait input time from astb t dstwt v dd = 5.0 v 1.5t 40 ns v dd = 3.0 v 1.5t 60 ns wait hold time from astb t hstwth v dd = 5.0 v (0.5+n) t+5 ns v dd = 3.0 v (0.5+n) t+10 ns delay from astb to wait t dstwth v dd = 5.0 v (1.5+a) t 40 ns v dd = 3.0 v (1.5+a) t 60 ns wait input time from rd t drwtl v dd = 5.0 v t 40 ns v dd = 3.0 v t 60 ns wait hold time from rd t hrwt v dd = 5.0 v nt+5 ns v dd = 3.0 v nt+10 ns delay from rd to wait t drwth v dd = 5.0 v (1+n) t 40 ns v dd = 3.0 v (1+n) t 60 ns data input time from wait t dwtid v dd = 5.0 v 0.5t 5ns v dd = 3.0 v 0.5t 10 ns delay from wait to rd t dwtr v dd = 5.0 v 0.5t ns v dd = 3.0 v 0.5t ns delay from wait to wr t dwtw v dd = 5.0 v 0.5t ns v dd = 3.0 v 0.5t ns wait input time from wr t dwwtl v dd = 5.0 v t 40 ns v dd = 3.0 v t 60 ns wait hold time from wr t hwwt v dd = 5.0 v nt+5 ns v dd = 3.0 v nt+10 ns delay from wr to wait t dwwth v dd = 5.0 v (1+n) t 40 ns v dd = 3.0 v (1+n) t 60 ns remarks 1. t: t cyk = 1/f clk (f clk : internal system clock cycle) 2. a: 1 during address wait; otherwise 0 3. n: number of wait states (n 0) 4. calculated as t = 79 ns (min.) @ v dd = 5.0 v 5. calculated as t = 159 ns (min.) @ v dd = 3.0 v
80 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a ac characteristics (t a = ?0 to +85 c, v dd = av dd = 3.0 to 5.5 v, v ss = av ss = 0 v) (3) bus hold/refresh timing parameter symbol conditions min. typ. max. unit delay from hldrq to float t fhqc v dd = 5.0 v (2+4+a+n) t+50 ns v dd = 3.0 v (2+4+a+n) t+50 ns delay from hldrq to t dhqhhah v dd = 5.0 v (3+4+a+n) t+30 ns hldak v dd = 3.0 v (3+4+a+n) t+40 ns delay from float to hldak t dcfha v dd = 5.0 v t+30 ns v dd = 3.0 v t+30 ns delay from hldrq to t dhqlhal v dd = 5.0 v 2t+40 ns hldak v dd = 3.0 v 2t+60 ns delay from hldak to active t dhac v dd = 5.0 v t 20 ns v dd = 3.0 v t 30 ns random read/write cycle time t rc v dd = 5.0 v 3t ns v dd = 3.0 v 3t ns refrq low-level pulse width t wrfql v dd = 5.0 v 1.5t 25 ns v dd = 3.0 v 1.5t 30 ns delay from astb to refrq t dstrfq v dd = 5.0 v 0.5t 9ns v dd = 3.0 v 0.5t 9ns delay from rd to refrq t drrfq v dd = 5.0 v 1.5t 9ns v dd = 3.0 v 1.5t 9ns delay from wr to refrq t dwrfq v dd = 5.0 v 1.5t 9ns v dd = 3.0 v 1.5t 9ns delay from refrq to astb t drfqst v dd = 5.0 v 0.5t 9ns v dd = 3.0 v 0.5t 9ns refrq high-level pulse width t wrfqh v dd = 5.0 v 1.5t 25 ns v dd = 3.0 v 1.5t 30 ns remarks 1. t: t cyk = 1/f clk (f clk : internal system clock cycle) 2. a: 1 during address wait; otherwise 0 3. n: number of wait states (n 0) 4. calculated as t = 79 ns (min.) @ v dd = 5.0 v 5. calculated as t = 159 ns (min.) @ v dd = 3.0 v
81 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a timing waveform (1) read operation (2) write operation astb a8 to a19 ad0 to ad7 rd t wsth t sast t dstid t hstla t drst t fra t drid t dar t wrl t dstr t daid t hra t dra t hrid astb a8 to a19 ad0 to ad7 wr t wsth t sast t hstla t dwst t daw t dstw t hwod t dstod t dwod t sodwr t wwl t hwa
82 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a hold timing external wait signal input timing (1) read operation (2) write operation hldrq hldak t dhqhhah t fhqc t dcfha t dhac t dhqlhal astb, a8 to a19, ad0 to ad7, rd, wr astb a8 to a19 ad0 to ad7 rd wait t dstwt t hstwth t dstwth t dawt t dwtid t dwtr t drwtl t hrwt t drwth astb a8 to a19 ad0 to ad7 wr wait t dstwt t hstwth t dstwth t dawt t dwtw t dwwtl t hwwt t dwwth
83 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a refresh timing waveform (1) random read/write cycle (2) when refresh memory is accessed for a read and write at the same time (3) refresh after a read (4) refresh after a write astb wr rd t rc t rc t rc t rc t rc t wrfql astb rd, wr refrq t dstrfq t drfqst t wrfqh astb rd refrq t drfqst t drrfq t wrfql astb wr refrq t drfqst t dwrfq t wrfql
84 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a serial operation (t a = ?0 to +85 c, v dd = av dd = 3.0 to 5.5 v, v ss = av ss = 0 v) (a) csi0, csi3 3-wire serial i/o mode (sck0, sck3 ... external clock input) parameter symbol conditions min. max. unit sck cycle time t cysk0 , so0 and so3 are f clk = f xx 8/f xx ns (sck0, sck3) t cysk3 cmos outputs except f clk = f xx 4/f clk ns sck low-level width t wskl0 , so0 and so3 are f clk = f xx 4/f xx 40 ns (sck0, sck3) t wskl3 cmos outputs except f clk = f xx 2/f clk 40 ns sck high-level width t wskh0 , so0 and so3 are f clk = f xx 4/f xx 40 ns (sck0, sck3) t wskh3 cmos outputs except f clk = f xx 2/f clk 40 ns si0, si3 setup time t sssk0 ,80ns (to sck0, sck3 )t sssk3 si0, si3 hold time t hssk0 , 1/f clk +80 ns (from sck0, sck3 )t hssk3 output delay time from t dbsk0 , cmos output 0 1/f clk +150 ns sck0, sck3 t dbsk3 n-ch open-drain output r l = 1 k ? 0 1/f clk +400 ns so0, so3 output hold time t hsbsk0 , when data is transferred 0.5t cysk0 40, ns (from sck0, sck3 )t hsbsk3 0.5t cysk3 40 remarks 1. the values in this table are those when cl = 100 pf. 2. f xx : external oscillator frequency (f xx = 12.58 mhz or f xx = 6.29 mhz) 3. f clk : system clock oscillation frequency (selectable from f xx , f xx /2, f xx /4, and f xx /8 by the standby control register (stbc)) (b) csi0, csi3 3-wire serial i/o mode (sck0, sck3 ... internal clock output) parameter symbol conditions min. max. unit sck cycle time t cysk0 , so0 and so3 are except f clk = f xx /8 8/f xx ns (sck0, sck3) t cysk3 cmos outputs f clk = f xx /8 16/f xx ns sck low-level width t wskl0 , so0 and so3 are except f clk = f xx /8 4/f xx 40 ns (sck0, sck3) t wskl3 cmos outputs f clk = f xx /8 8/f xx 40 ns sck high-level width t wskh0 , so0 and so3 are except f clk = f xx /8 4/f xx 40 ns (sck0, sck3) t wskh3 cmos outputs f clk = f xx /8 8/f xx 40 ns si0, si3 setup time t sssk0 ,80ns (to sck0, sck3 )t sssk3 si0, si3 hold time t hssk0 ,80ns (from sck0, sck3 )t hssk3 output delay time from t dbsk0 , cmos output 0 150 ns sck0, sck3 t dbsk3 n-ch open-drain output r l = 1 k ? 0 400 ns so0, so3 output hold time t hsbsk0 , when data is transferred 0.5t cysk0 40, ns (from sck0, sck3 )t hsbsk3 0.5t cysk3 40 remarks 1. the values in this table are those when cl = 100 pf. 2. f xx : external oscillator frequency (f xx = 12.58 mhz or f xx = 6.29 mhz) 3. f clk : system clock oscillation frequency (selectable from f xx , f xx /2, f xx /4, and f xx /8 by the standby control register (stbc))
85 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a serial operation (t a = ?0 to +85 c, v dd = av dd = 3.0 to 5.5 v, v ss = av ss = 0 v) (c) uart0, uart3 (asynchronous serial interface mode) parameter symbol conditions min. typ. max. unit asck0, asck2 cycle time t cyask 4.0 v dd 5.5 v 160 ns 320 ns asck0, asck2 low-level width t waskl 4.0 v dd 5.5 v 65 ns 120 ns asck0, asck2 high-level width t waskh 4.0 v dd 5.5 v 65 ns 120 ns
86 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a serial operation (t a = ?0 to +85 c, v dd = av dd = 3.0 to 5.5 v, v ss = av ss = 0 v) (d) ioe1, ioe2 3-wire serial i/o mode (sck1, sck2 ... external clock input) parameter symbol conditions min. max. unit sck cycle time (sck1, sck2) t cysk1 4.0 v dd 5.5 v 640 ns t cysk2 1280 ns sck low-level width t wskl1 , 4.0 v dd 5.5 v 280 ns (sck1, sck2) t wskl2 600 ns sck high-level width t wskh1 , 4.0 v dd 5.5 v 280 ns (sck1, sck2) t wskh2 600 ns si1, si2 setup time t sssk1 ,40ns (to sck1, sck2 )t sssk2 si1, si2 hold time t hssk1 ,40ns (from sck1, sck2 )t hssk2 output delay time from t dsosk1 ,050ns sck1, sck2 t dsosk2 so1, so2 output hold time t hsosk1 , when data is transferred 0.5t cysk1 40, ns (from sck1, sck2 )t hsosk2 0.5t cysk2 40 remarks 1. the values in this table are those when cl = 100 pf. 2. t: selected serial clock cycle. the minimum value is 8/f xx . (e) ioe1, ioe2 3-wire serial i/o mode (sck1, sck2 ... internal clock output) parameter symbol conditions min. max. unit sck cycle time (sck1, sck2) t cysk1 tns t cysk2 sck low-level width t wskl1 , 0.5t 40 ns (sck1, sck2) t wskl2 sck high-level width t wskh1 , 0.5t 40 ns (sck1, sck2) t wskh2 si1, si2 setup time t sssk1 ,40ns (to sck1, sck2 )t sssk2 si1, si2 hold time t hssk1 ,40ns (from sck1, sck2 )t hssk2 output delay time from t dsosk1 ,050ns sck1, sck2 t dsosk2 so1, so2 output hold time t hsosk1 , when data is transferred 0.5t cysk1 40, ns (from sck1, sck2 )t hsosk2 0.5t cysk2 40 remarks 1. the values in this table are those when cl = 100 pf. 2. t: selected serial clock cycle. the minimum value is 8/f xx .
87 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a other operations (t a = ?0 to +85 c, v dd = av dd = 3.0 to 5.5 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit nmi high-/low-level width t wnil 10 s t wnih intp0 high-/low-level width t wit0l 4t cysmp s t wit0h intp0 to intp3, ci high-/ t wit1l 4t cycpu s low-level width t wit1h intp4, intp5 high-/ t wit2l 10 s low-level width t wit2h reset high-/low-level t wrsl 10 s width note t wrsh note when the power is turned on or when stop mode is released by reset, secure the oscillation stabilization wait time while the reset is at a low-level width. when the power is turned on, be sure to activate v dd in the reset = low-level state. remark t cysmp : sampling clock set by software t cycpu : cpu clock set by software in the cpu clock output operation (t a = ?0 to +85 c, v dd = av dd = 3.0 to 5.5 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit clkout cycle time t cycl nt 79 32000 ns clkout low-level width t cll 4.5 v dd 5.5 v 0.5t 10 ns 0.5t 20 ns clkout high-level width t clh 4.5 v dd 5.5 v 0.5t 10 ns 0.5t 20 ns clkout rise time t clr 4.5 v dd 5.5 v 10 ns 3.0 v dd 4.5 v 20 ns clkout fall time t clf 4.5 v dd 5.5 v 10 ns 3.0 v dd 4.5 v 20 ns remark n: division ratio of clock output frequency, t: t cyk = 1/f clk (system clock cycle time) iebus controller characteristics (t a = ?0 to +85 c, v dd = av dd = 4.5 to 5.5 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit iebus system clock frequency f s mode 1 6.29 mhz remark although the system clock frequency in the iebus specifications is 6.0 mhz, in the pd784938a, operation at 6.29 mhz is also guaranteed. note, however, that operation at 6.0 mhz and 6.29 mhz cannot be used together.
88 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a a/d converter characteristics (t a = ?0 to +85 c, v dd = av dd = av ref1 = 3.0 to 5.5 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 8 bit overall error note iead = 00h 6.29 mhz f xx 12.58 mhz 0.6 %fsr note 2 and other than fr = 1 6.29 mhz f xx 12.58 mhz 1.5 %fsr note 2 and fr = 1 iead = 01h 4.5 v dd 5.5 v 1 2.2 %fsr note 2 3.0 v dd 5.5 v 1.4 2.6 %fsr note 2 quantization error 1/2 lsb conversion time t conv fr = 1 : 120 t cyk 9.5 480 s fr = 0 : 240 t cyk 19.1 960 s sampling time t samp fr = 1 : 18 t cyk 1.4 72 s fr = 0 : 36 t cyk 2.9 144 s analog input voltage v ian av ss av ref1 v analog input impedance r an 1000 m ? reference voltage av ref1 3.0 av dd v av ref1 resistor r avref1 3.0 10 k ? av ref1 current ai ref1 0.5 1.5 ma av dd current ai dd1 2.0 5.0 ma ai dd2 20 ma notes 1. excludes quantization error ( 1/2 lsb). 2. it is indicated as a ratio (%fsr) to the full-scale value. caution the analog input pins of the pd784938a function alternately as the port 7 pins (i/o port pins). however when using the a/d converter, it is necessary to set all the pins of port 7 to input mode in order to prevent data from being inverted by the output port operation, thus degrading the a/d conversion accuracy. at this time, pins cannot be used as output ports even though they are not used as a/d analog input port.
89 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a sck0, sck3 si0, si3 so0, so3 output data input data t ssskn t hsskn t dsbskn t wskln t wskhn t hsbskn t cyskn sck1, sck2 si1, si2 so1, so2 output data input data t sssk1 t hssk1 t dsosk t hsosk t wskl1 t wskh1 t cysk1 asck0, asck2 t waskh t waskl t cyask clkout t clh t cll t cycl t clf t clr serial operation (csi, csi3) n = 0, 3 serial operation (ioe1, ioe2) serial operation (uart0, uart2) clock output timing
90 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a nmi intp0 ci, intp1 to intp3 intp4, intp5 t wnih t wnil t wit0h t wit0l t wit1h t wit1l t wit2h t wit2l reset t wrsh t wrsl interrupt request input timing reset input timing
91 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a v dd reset nmi (clearing by falling edge) nmi (clearing by rising edge) t hvd t fvd t rvd t drel v dddr stop mode setting t wait data retention characteristics
92 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a 17. package drawings remark the external dimensions and material of the es version are the same as those of the mass-produced version. 100pin plastic qfp (14x20) item millimeters inches note each lead centerline is located within 0.15 mm (0.006 inch) of its true position (t.p.) at maximum material condition. p100gf-65-3ba1-3 b 20.00.2 0.795 +0.009 0.008 c 14.00.2 0.551 +0.009 0.008 d 17.60.4 0.6930.016 f 0.8 0.031 g 0.6 0.024 h 0.300.10 0.012 i 0.15 0.006 j 0.65 (t.p.) 0.026 (t.p.) k 1.80.2 0.071 +0.008 0.009 l 0.80.2 0.031 n 0.10 0.004 q 0.10.1 0.0040.004 s 3.0 max. 0.119 max. detail of lead end r q j k m l n p g f h i m p 2.70.1 0.106 +0.005 0.004 80 81 50 100 1 31 30 51 b a cd s a 23.60.4 0.9290.016 m 0.15 0.006 +0.10 0.05 r5 5 5 5 +0.004 0.005 +0.009 0.008 +0.004 0.003
93 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a 18. recommended soldering conditions the pd784938a should be soldered and mounted under the following recommended conditions. for details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact an nec sales representative. table 18-1. surface mounting type soldering conditions pd784935agf- -3ba: 100-pin plastic qfp (14 20) pd784936agf- -3ba: 100-pin plastic qfp (14 20) pd784937agf- -3ba: 100-pin plastic qfp (14 20) pd784938agf- -3ba: 100-pin plastic qfp (14 20) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 sec. max. (at 210 c or higher), ir35-00-2 count: two times or less vps package peak temperature: 215 c, time: 40 sec. max. (at 200 c or higher), vp15-00-2 count: two times or less wave soldering solder bath temperature: 260 c max., time: 10 sec. max., count: once, ws60-00-1 preheating temperature: 120 c max. (package surface temperature) partial heating pin temperature: 300 c max., time: 3 sec. max. (per pin row) caution do not use different soldering methods together (except for partial heating).
94 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a appendix a. development tools the following development tools are available for system development using the pd784938a. also refer to (5) cautions on using development tools . (1) language processing software ra78k4 assembler package common to 78k/iv series cc78k4 c compiler package common to 78k/iv series df784937 device file for pd784938a subseries cc78k4-l c compiler library source file common to 78k/iv series (2) flash memory writing tools flashpro iii note flash programmer for microcontroller with flash memory (pg-fp iii) fa-100gf flash memory writing adapter for 100-pin plastic qfp (gf-3ba type). wiring must be performed according to the product used. note under development (3) debugging tools when ie-78k4-ns in-circuit emulator is used ie-78k4-ns in-circuit emulator common to 78k/iv series ie-70000-mc-ps-b power supply unit for ie-78k4-ns ie-70000-98-if-c interface adapter used when pc-9800 series (except notebook type) is used as host machine ie-70000-cd-if-c pc card and cable used when pc-9800 series notebook type pc is used as host machine ie-70000-pc-if-c interface adapter used when ibm pc/at tm or compatible is used as host machine ie-784937-ns-em1 emulation board to emulate pd784938a subseries np-100gf emulation probe for 100-pin plastic qfp (gf-3ba type) ev-9200gf-100 socket to be mounted on a target system board made for 100-pin plastic qfp (gf-3ba type) id78k4-ns integrated debugger for ie-78k4-ns sm78k4 system simulator common to 78k/iv series df784937 device file for pd784938a subseries
95 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a when ie-784000-r in-circuit emulator is used ie-784000-r in-circuit emulator common to 78k/iv series ie-70000-98-if-b interface adapter used when pc-9800 series (except notebook type) is used as host machine ie-70000-98-if-c ie-70000-98n-if interface adapter and cable used when pc-9800 series notebook type pc is used as host machine ie-70000-pc-if-b interface adapter used when ibm pc/at or compatible is used as host machine ie-70000-pc-if-c ie-78000-r-sv3 interface adapter and cable used when ews is used as host machine ie-784937-ns-em1 emulation board to emulate pd784938a subseries ie-784000-r-em emulation board common to 78k/iv series ie-78k4-r-ex2 emulation probe conversion board necessary when using ie-784937-ns-em1 on ie-784000-r. not necessary when using ie-784937-r-em1 ep-78064gf-r emulation probe for 100-pin plastic qfp (gf-3ba type) ev-9200gf-100 socket to be mounted on a target system board made for 100-pin plastic qfp (gf-3ba type) id78k4 integrated debugger for ie-784000-r sm78k4 system simulator common to 78k/iv series df784937 device file for pd784938a subseries (4) real-time os rx78k/iv real-time os for 78k/iv series mx78k4 os for 78k/iv series
96 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a (5) cautions on using development tools the id78k4-ns, id78k4, and sm78k4 are used in combination with the df784937. the cc78k4 and rx78k/iv are used in combination with the ra78k4 or df784937. the flashpro iii, fa-100gf, and np-100gf are products made by naito densei machida mfg. co, ltd (tel +81-44-822-3813). the host machine and os suitable for each software are as follows: host machine [os] pc ews pc-9800 series [windows] hp9000 series 700 tm [hp-ux tm ] ibm pc/at and compatibles sparcstation tm [sunos tm , solaris tm ] software [japanese/english windows] news tm (risc) [news-os tm ] ra78k4 note cc78k4 note id78k4-ns id78k4 ? sm78k4 rx78k/iv note mx78k4 note note dos-based software
97 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a appendix b. related documents documents related to devices document name document number pd784935a, 784936a, 784937a, 784938a data sheet this document pd78f4937 preliminary product information u13573e pd784938a subseries user s manual - hardware u13987e 78k/iv series user s manual - instructions u10905e 78k/iv series application note - software basics u10095e documents related to development tools (user s manuals) document name document number ra78k4 assembler package language u11162e operation u11334e ra78k4 structured assembler preprocessor u11743e cc78k4 c compiler language u11571e operation u11572e ie-78k4-ns u13556e ie-784000-r u12903e ie-784937-r-em1 planned ie-784937-ns-em1 planned ep-78064 eeu-1469 sm78k4 system simulator - windows based reference u10093e sm78k series system simulator external part user open u10092e interface specifications id78k4-ns integrated debugger reference u12796e id78k4 integrated debugger - windows based reference u10440e id78k4 integrated debugger - hp-ux, sunos, news-os based reference u11960e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
98 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a documents related to embedded software (user s manuals) document name document number 78k/iv series real-time os fundamental u10603e installation u10604e other documents document name document number semiconductor selection guide products & packages (cd-rom) x13769x semiconductor device mounting technology manual c10535e quality grades on nec semiconductor devices c11531e nec semiconductor device reliability/quality control system u10983e guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
99 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a [memo]
100 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. eeprom, fip, and iebus are trademarks of nec corporation. windows is either a registered trademark or a trademark of microsoft corporation in the united states and/ or other countries. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademarks of sun microsystems, inc. news and news-os are trademarks of sony corporation.
101 data sheet u13572ej2v0ds pd784935a,784936a,784937a,784938a regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. madrid office madrid, spain tel: 91-504-2787 fax: 91-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division guarulhos-sp brasil tel: 55-11-6462-6810 fax: 55-11-6462-6829 j00.7
m pd784935a,784936a,784937a,784938a the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. m8e 00. 4 the information in this document is current as of september, 2000. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above).

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